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619 Commits 7 Branches 1 Tag
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619 Commits

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Author SHA1 Message Date
Andreas Olofsson
dccaadc286 Updating register names and fixing error in description of RXCFG 2015-11-11 14:26:46 -05:00
Andreas Olofsson
1ddbc4c0a8 Adding missing register 2015-11-11 14:26:35 -05:00
Andreas Olofsson
038d39def7 Defparam typo 
- Not caught by iverilog!! (file bug??)
- Caught by Vivado.
 2015-11-11 14:13:38 -05:00
Andreas Olofsson
867b750c50 Adding write from stimulus to dv link1 
- also, more cleanup of ID parameters
 2015-11-11 14:02:02 -05:00
Andreas Olofsson
c885745f6c Fixing half/byte zero-out bug 
- Interrupted mid coding apparently..
- Upper bits need to be zeroed out for 8/16 bit read responses
 2015-11-11 14:00:13 -05:00
Andreas Olofsson
d788e0da2d Fixing alignment issue on write 
-The epiphany chip memory does alignment on write
 2015-11-11 13:59:24 -05:00
Andreas Olofsson
4885c3f7d2 Adding byte/halfword test 2015-11-11 13:58:55 -05:00
Andreas Olofsson
0a2ea66b7e Bug fix. Adding missing ID parameter. 
- would only show up at different ID
- better to always make defauly nonsense
- sneaky...
 2015-11-11 13:58:04 -05:00
Andreas Olofsson
9c1fb038a9 Adding test for remapping logic 2015-11-11 13:57:18 -05:00
Andreas Olofsson
3f0efb9db2 Adding dummy.elf for bootgen 2015-11-11 13:56:48 -05:00
Andreas Olofsson
464700c0b9 Adding converter script for bootgen 2015-11-11 13:56:09 -05:00
Andreas Olofsson
bb084f1670 Adding skeleton for adi sdr design 
Now need to integrate elink in this
 2015-11-11 00:42:14 -05:00
Andreas Olofsson
9feaa36dce Refactoring and adding some tests 
- "infinite loop test"
- separating out common elink functions
-
 2015-11-11 05:32:06 +00:00
Andreas Olofsson
ce7c19ef0c Merge branch 'master' of https://github.com/parallella/oh 2015-11-11 05:31:23 +00:00
Andreas Olofsson
69d481b8f0 Merge branch 'master' of https://github.com/parallella/oh 2015-11-11 00:30:58 -05:00
Andreas Olofsson
62305244e9 Build script fixup + gitignore 
- Filtering "src" wasn't such a good idea...
- Fixing script for bitstream, bootgen doesn't overwrite existing bit stream files (thanks Xilinx, cost me an hour of anxiety!!)
 2015-11-11 00:29:15 -05:00
Andreas Olofsson
e3544c4fc8 Adding toggle led test 2015-11-11 03:41:22 +00:00
Andreas Olofsson
b1e3a39d06 adding legacy mode registers 2015-11-11 03:39:17 +00:00
Andreas Olofsson
e097da6bda Removing reset sequence from access utility 
- Responsibility of application
- Makes no sense resettting device after each write/read..
 2015-11-11 03:36:55 +00:00
Andreas Olofsson
b2926fdc5e Adding test for setting east link to half speed 2015-11-10 22:30:41 -05:00
Andreas Olofsson
d2d291a0fc Merge branch 'master' of https://github.com/parallella/oh 2015-11-10 22:30:10 -05:00
Andreas Olofsson
7f0698bbc8 Fixed ctrlmode bug 
- Found this by trying to toggle the LED in hardware!!
- So freaking close!!
 2015-11-10 22:29:30 -05:00
Andreas Olofsson
6b2f6f42bc Added missing init() routine 
- Version 0 is the one currently in production, works!!!
- Now starting to debug the new linke (verion 1)
 2015-11-11 02:00:14 +00:00
Andreas Olofsson
f92bcb3f0b Adding elink register include file 2015-11-10 18:48:53 -05:00
Andreas Olofsson
8c4a02fbdf Adding bringup script for elink 
- uses 104 bit packet for formatting
- makes for easy transition from verilog testbench
- happy with this one...
 2015-11-10 17:01:04 -05:00
Andreas Olofsson
5840c3e369 Fixing reset bug 
- There is a register reset by out_clk reset on fifo_cdc
- This means the config path needs to us rx synched reset to be clean
 2015-11-10 09:19:45 -05:00
Andreas Olofsson
f2b2c4fd00 Balancing TXclocks 
- Better to be balanced with clocks (BUFG) than trying with BUFIO and having CDCs. Tools warned about it...
 2015-11-10 09:19:01 -05:00
Andreas Olofsson
04cd179f5a Lint fixes for icarus/verilator 2015-11-09 21:57:25 -05:00
Andreas Olofsson
243ba6b608 Speedpath fix for rx io 
- reduce fanout on IDDR block
 2015-11-09 21:56:46 -05:00
Andreas Olofsson
efef6448c2 Fixing wait bug on config write (2 bugs) 
- missing reset on wait signal
- missing wait on cfg
 2015-11-09 21:55:46 -05:00
Andreas Olofsson
ef204a875b Fixed register read/write test 
- Has been tested with dv_axi to work
 2015-11-09 20:39:57 -05:00
Andreas Olofsson
02ae7cf83d Cleanup 2015-11-09 20:39:48 -05:00
Andreas Olofsson
6dcd5e96bf Cleanup after lock width change for zynq axi 2015-11-09 20:39:16 -05:00
Andreas Olofsson
e2c917b6f9 Fixed packet reformatting bug 2015-11-09 20:38:55 -05:00
Andreas Olofsson
497dd71aaa Fixed readback bug 
- there were hard coded magic number in code, bad practice!
- now works!
 2015-11-09 20:38:12 -05:00
Andreas Olofsson
19f773839d Fixed bug with packet decode 
- mailbox write now working
 2015-11-09 20:37:17 -05:00
Andreas Olofsson
13d29f8e67 Stupid typos.. 2015-11-09 16:18:20 -05:00
Andreas Olofsson
61eb56c6f7 Final Vivado fixups: 
- reduced frame fanout, removed clock gater in erx_io (improves speed path)
- driving constants on "wid signals" (proper)
- making lock signal 1 bit wide to remove warning
- moved backed to BUFIO for IDDR blocks
 2015-11-09 16:09:12 -05:00
Andreas Olofsson
55ba8ff635 Cleaning up warnings from FGPA tools 
- removing unconnected ports
- only one rst input for async_fifo
- synchronizing the reset input toe emaxi fifo
 2015-11-09 13:23:40 -05:00
Andreas Olofsson
cf2123ce88 Don't generate fifo during packaging 2015-11-09 13:22:27 -05:00
Andreas Olofsson
c84e1c96b7 Adding hdmi pins for parallella 2015-11-09 13:22:08 -05:00
Andreas Olofsson
64f55eb792 Fix 0 day bug... 
- this shows why it's so important to read the warnings. (circuit was broken!)
 2015-11-09 13:21:26 -05:00
Andreas Olofsson
bf614a9873 Cleaning up fifo interface 
- removing redundant signals
- configuring to put synchronizer inside fifo
- one reset only (not two)
 2015-11-09 13:20:46 -05:00
Andreas Olofsson
01fd24e069 Fixing synchronization reset speed path 
- This seems silly, why even have a syncrhonizer
- Safe to set speed path?
 2015-11-09 00:16:35 -05:00
Andreas Olofsson
875e4213a5 Adding attributes to sync logic 
- Otherwise tool was throwing away logic and timing incorretly.
- This is why you HAVE to isolate this logic! Solve the problem once for all logic and for everyone.
 2015-11-08 23:30:47 -05:00
Andreas Olofsson
3797cac74f Solving critical paths for TX/RX 
- Using the BUFIO makes another clock domain....FPGAs apparently hate clock domain crossings, avoid them at all cost.
- Now moving back to having on high speed clock domain for logic and DDR blocks, take care of IO alignment in software for TX and RX
- Also, fixed the io_wait path with logic...not sure what I was thinking there. Logic was trivial. The way it was,the io path was going straight into the FIFO as a wait.
 2015-11-08 23:28:39 -05:00
Andreas Olofsson
405c322d75 Adding build shell script for headless 2015-11-08 07:33:16 -05:00
Andreas Olofsson
65f772ddef Fixing careless mistakes.. 2015-11-06 22:51:09 -05:00
Andreas Olofsson
9383f32764 Making sure ETYPE is set to 0. 2015-11-06 22:41:43 -05:00
Andreas Olofsson
aa940c2a39 Fixing typos 2015-11-06 22:40:59 -05:00