Andreas Olofsson
9fb9dc1cd5
Adding IP packaging script
2015-07-02 16:58:43 -04:00
Andreas Olofsson
9379484f65
Fifo parameter change
...
-Changing parameter name to DW
-Making depth 32 for axi interfaces
(tune this later...)
2015-07-02 16:55:42 -04:00
Andreas Olofsson
f1b37ab4c4
Ephycard should not be default
2015-07-02 16:54:31 -04:00
Andreas Olofsson
d6f61784b0
Update dv paths
...
-includes inside files (methodology change)
-adding ip paths
2015-07-02 16:48:14 -04:00
Andreas Olofsson
e28cd3cb97
Adding search path for include file
2015-07-02 16:47:07 -04:00
Andreas Olofsson
368836ab9b
Adding back a better fufu test vector
2015-07-02 16:46:33 -04:00
Andreas Olofsson
0c66100d6d
Adding half full signal to fifo
2015-07-02 15:00:18 -04:00
Andreas Olofsson
51a642a7b7
Adding 32 deep interface fifo for AXI
...
-needed to support burst properly
2015-07-02 14:59:57 -04:00
Andreas Olofsson
c0f5c23cb0
Merge pull request #6 from plindstroem/patrik
...
Patrik
2015-07-02 09:26:22 -04:00
Patrik Lindström
a20c9f25ec
clean up
2015-07-02 15:01:33 +02:00
Patrik Lindström
b9558a70c8
change path
2015-07-02 14:53:21 +02:00
Patrik Lindström
4a749bf2d8
timing fixes
2015-07-01 00:14:46 +02:00
Patrik Lindström
6d13611f21
script fixes
2015-06-30 16:02:39 +02:00
Patrik Lindström
7b1e712884
script fixes
2015-06-30 15:00:32 +02:00
Patrik Lindström
667c7cb6a8
script fixes
2015-06-30 14:56:27 +02:00
Patrik Lindström
d0d6cc0d4a
Fixed file locations
2015-06-30 14:12:04 +02:00
Patrik Lindström
a284dff462
Bug fixes
2015-06-30 14:04:16 +02:00
Patrik Lindström
6a232d7834
adding project folder
2015-06-30 13:58:20 +02:00
Patrik Lindström
634ff371ac
Bug fixes
2015-06-30 13:32:05 +02:00
Patrik Lindström
48fdf2d782
Added iostandard parameter
2015-06-30 12:44:22 +02:00
Patrik Lindström
f232d9d297
Changed rx_ref_clk PLL divider
2015-06-30 12:35:38 +02:00
Patrik Lindström
8c0dbffb61
Added different IDW for m_axi and s_axi
2015-06-30 12:31:14 +02:00
Andreas Olofsson
537bb6a330
Cleanup
2015-06-25 22:14:19 -04:00
Andreas Olofsson
e960b6f7c0
Adding IP package reference script
2015-06-25 22:14:05 -04:00
Andreas Olofsson
fc31ad57fd
Reorg
2015-06-25 19:52:28 -04:00
Andreas Olofsson
d9155f6538
Placeholder for elink
2015-06-25 16:17:20 -04:00
Andreas Olofsson
eb7028fdbf
Reorg
2015-06-25 16:13:20 -04:00
Andreas Olofsson
badac2aa76
Name changes for signal grouping
2015-06-25 16:09:05 -04:00
Andreas Olofsson
b0c7b75407
Adding OBUF model
2015-06-25 15:42:20 -04:00
Andreas Olofsson
2cbf91b07b
Making reset sync in emmu
2015-05-23 22:26:15 -04:00
Andreas Olofsson
7b8a9cf474
Adding IP file for async fifo
...
-This is the place for all generic IP blocks
2015-05-23 22:24:44 -04:00
Andreas Olofsson
bc53400888
Adding parallella block design
...
-Start with gui
-Generate block design
-Edit text, this is f'ing crazy!
-If this is the only way to use the vivado IP not sure I want it
-Strive towards doing everything in verilog
-Split into:
1.) Verilog block (no IP!)
2.) One top level to instantiate IP + clean verilog block
-Never fight the tools..
2015-05-22 21:38:39 -04:00
Andreas Olofsson
c9f64a2fb2
Fixing dv to check axi_elink
...
-Need to split these, getting too cumbersome
2015-05-21 22:56:23 -04:00
Andreas Olofsson
1eb2bcea89
Removing custom xilinx primitives
...
-Using the memory_sp macro instead...
-Cleaner design
-axi_elink now works!
2015-05-21 22:54:29 -04:00
Andreas Olofsson
24d824f080
Fixing read response address
...
-using `define from elink_regmap (ie 'D')
2015-05-20 15:04:29 -04:00
Andreas Olofsson
7f0f858b92
Letting read response packets through
...
-Needed for loopback testing
2015-05-20 15:03:22 -04:00
Andreas Olofsson
a60de7fb30
Adding readback on axi_elink
...
-Another cludgy memory
-Note that current esaxi doesn't support pushback so we have to hack the test to avoid read/write contention on this port.
2015-05-19 23:53:05 -04:00
Andreas Olofsson
b1c3b3fb8c
Adding filtering to ecfg_if
...
-Avoids garbage writing coming back to esaxi
2015-05-19 23:52:00 -04:00
Andreas Olofsson
005c9872dd
Removing timeout from logic
...
-Should be direct interface to esaxi
2015-05-19 23:51:17 -04:00
Andreas Olofsson
7d524d0f68
Changing axi interface <--> elink protocol
...
-Now consistant with packet, access, wait protocol
2015-05-19 22:08:41 -04:00
Andreas Olofsson
8d3cbf8257
Clean axi_elink module
...
-Clocks included inside for easy integration
-Another version might have the clocks and reset as inputs instead
2015-05-19 22:07:16 -04:00
Andreas Olofsson
6d9731f14a
Including environment for axi_elink
...
-Should probably split this into separate environments
-Getting bulky and ugly...
2015-05-19 22:06:15 -04:00
Andreas Olofsson
815db5669e
Merge branch 'master' of https://github.com/parallella/oh
2015-05-18 15:39:42 -04:00
Andreas Olofsson
451a1fa925
MILESTONE: Bursts working!!!
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-Fairly clean minimalist design
-Complete redesign
-Need to do random read/write testing to make sure
-Speed?
2015-05-18 15:38:30 -04:00
Andreas Olofsson
665876cfb4
Adding bursting to test bench
2015-05-18 15:37:46 -04:00
Andreas Olofsson
3ff0d56057
Deleting MIT license for now to avoid confusion.
...
Everything is GPL until further notice
2015-05-18 12:16:17 -04:00
Andreas Olofsson
41f97e45ff
Converting to synchronous reset
2015-05-17 23:00:53 -04:00
Andreas Olofsson
ae8d4b4dcd
Adding more reports
...
-check_timing is a crucial summary
2015-05-17 22:35:15 -04:00
Andreas Olofsson
559ffcc6e0
File name changes and additions
2015-05-17 22:34:42 -04:00
Andreas Olofsson
6485d1a9e7
Adding input delay constraints for RX
...
-doesn't meet timing
-needs work...
2015-05-17 22:33:42 -04:00
