Andreas Olofsson
7418d45f5e
Cleanup
...
-Packet interface change
-Adding RX enable logic with synchronizer (better place than erx_io)
2015-04-23 17:59:36 -04:00
Andreas Olofsson
d9525b6ae4
Major upgrade
...
-Adding DMA, EMMU, CFG
-Removing redundant signals
-Changing to packet interface
2015-04-23 17:58:18 -04:00
Andreas Olofsson
9a614d1094
Packet interface change
2015-04-23 17:57:24 -04:00
Andreas Olofsson
44f162ec09
Packet interface change
...
-Changed packet interface
-Removed rd/wr from block, was pass through
2015-04-23 17:56:15 -04:00
Andreas Olofsson
31e721cea7
Interface change
...
Changed to packet interface
Changed name to "mailbox"
2015-04-23 17:54:59 -04:00
Andreas Olofsson
8266e6dd29
Changing to packet interface
2015-04-23 17:54:23 -04:00
Andreas Olofsson
34813035bc
Changing FIFO interface
...
More inline with standard Xilinx fifo
names, names, names..ugh
2015-04-23 17:53:22 -04:00
Andreas Olofsson
62c2c0e654
Adding comments
2015-04-23 17:52:46 -04:00
Andreas Olofsson
35d6c3934f
Comments
2015-04-23 17:52:06 -04:00
Andreas Olofsson
1e1644138e
Splitting register file (rx,tx,base)
...
The goal is to have 100% independence in RX and TX pipes
2015-04-23 17:50:45 -04:00
Andreas Olofsson
0d10fbd26f
Adding more docs
2015-04-23 17:50:16 -04:00
Andreas Olofsson
028fac446e
Adding an emesh DMA
2015-04-23 17:49:06 -04:00
Andreas Olofsson
8770696d87
Massive commit sequence coming...
2015-04-23 17:48:12 -04:00
Andreas Olofsson
2b22d1c4af
Adding emesh to packet converters
...
-getting tired of all the typing after all....
2015-04-22 16:43:52 -04:00
Andreas Olofsson
cc5f165454
Clarified lclk names
2015-04-22 15:03:24 -04:00
Andreas Olofsson
c225349639
Updated clocking diagram
2015-04-22 15:02:50 -04:00
Andreas Olofsson
703da8445b
deleted junk
2015-04-22 15:02:31 -04:00
Andreas Olofsson
bc71401888
Adding elink clocking diagram
2015-04-22 13:58:51 -04:00
Andreas Olofsson
797d836a02
Renaming constants file
2015-04-22 13:56:48 -04:00
Andreas Olofsson
617214cc90
Cleanup
2015-04-22 13:56:29 -04:00
Andreas Olofsson
77d41cfe4e
Adding PLL and MMCME2 primitives
2015-04-22 13:55:59 -04:00
Andreas Olofsson
1508afa2ea
Adding a "max" ps7 system for reference
...
Not convinced that it's good to do this in text...
(but it's always good to know what's underneath the hood)
Vivado IP generates wrappers after all
2015-04-22 13:54:52 -04:00
Andreas Olofsson
fce122565d
Adding README file for xilibs
2015-04-21 21:52:20 -04:00
Andreas Olofsson
ba8f400a37
oops
2015-04-21 21:50:03 -04:00
Andreas Olofsson
c01a9fbd27
Adding basic readme files
2015-04-21 21:49:40 -04:00
Andreas Olofsson
f35ed3836d
Only primitiveds in the xilibs (no generated IP)
2015-04-21 21:44:44 -04:00
Andreas Olofsson
ebaac22700
Cleanup
2015-04-21 21:43:16 -04:00
Andreas Olofsson
8954d14b92
Basic infrastructure
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-GPL license file
-Need to add license section in README file...
2015-04-21 21:36:37 -04:00
Andreas Olofsson
275264c84d
Reorg
2015-04-21 21:33:49 -04:00
Andreas Olofsson
e437297991
Merge branch 'master' of https://github.com/parallella/oh
...
Conflicts:
README.md
2015-04-21 21:22:30 -04:00
Andreas Olofsson
a717a3b744
Update README.md
2015-04-21 21:19:10 -04:00
Andreas Olofsson
83dea660a2
Update README.md
2015-04-21 21:17:02 -04:00
Andreas Olofsson
b988a54244
Initial commit
2015-04-21 21:16:42 -04:00
Andreas Olofsson
035b3c9ba5
Milestone: WRITE AND READ FROM HOST WORKS!
2015-04-21 17:16:20 -04:00
Andreas Olofsson
b89d6222d8
Adding test for readback from host
2015-04-21 17:15:56 -04:00
Andreas Olofsson
d0b04687ea
Bug fix, missing pipeline stage on read response
...
-Apparantly old FIFO was not pipelined (IE data comes back same cycle).
-Not knowing the Xilinx logic, I made it a regular one cycle pipeline
memory based FIFO
2015-04-21 17:14:30 -04:00
Andreas Olofsson
fc3926ceb1
Added wait signal for reads
2015-04-21 17:13:53 -04:00
Andreas Olofsson
0d42736914
Implemented enesh memory
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-not parametrized
-keeping 64 bit wide for now
2015-04-21 17:13:09 -04:00
Andreas Olofsson
7685e297fb
Rename
2015-04-21 17:12:52 -04:00
Andreas Olofsson
2369e92ffa
Bug fix, missing "data hold" stage
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Hadn't realized that the data needed to be held
Need to look at this logic again!
For now going back to old logic
2015-04-21 17:10:51 -04:00
Andreas Olofsson
046294778c
Wrong port direction on output
2015-04-21 17:10:22 -04:00
Andreas Olofsson
e033e233d0
Integrating emesh memory module
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-This will flush out the final read response path
2015-04-20 23:07:13 -04:00
Andreas Olofsson
6a6f953986
Adding emesh memory module (empty for now)
2015-04-20 23:06:49 -04:00
Andreas Olofsson
4c44c59079
Message box working...
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-More testing needed!
2015-04-19 21:55:07 -04:00
Andreas Olofsson
7e44dfc84c
Memory read bug (clk floating)
2015-04-19 21:54:22 -04:00
Andreas Olofsson
6cc5d6de90
MMU working...
...
-Needs more testing
2015-04-19 21:36:47 -04:00
Andreas Olofsson
7c93c565e9
Adding back awid, arid, lock to AXI interface
2015-04-18 17:35:22 -04:00
Andreas Olofsson
44a4d0e669
Adding gtkwave signals file
2015-04-18 16:42:34 -04:00
Andreas Olofsson
9e931c47ec
Cleanup
2015-04-18 16:26:32 -04:00
Andreas Olofsson
f141a0e320
Clock cleanup
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-Adding enable signal to clock out. Definitely right decision to keep
separate bit from the divider field.
-Fixed settings for to fit new register field
-XILINX version is still broken!!
2015-04-18 16:24:26 -04:00
