FPGA/oh
1
0
Fork 0
mirror of https://github.com/aolofsson/oh.git synced 2025-01-30 02:32:53 +08:00
Code Issues Projects Releases Wiki Activity
166 Commits 7 Branches 1 Tag
Commit Graph

4 Commits

Author SHA1 Message Date
Andreas Olofsson
44f162ec09 Packet interface change 
-Changed packet interface
-Removed rd/wr from block, was pass through
 2015-04-23 17:56:15 -04:00
Andreas Olofsson
cc5f165454 Clarified lclk names 2015-04-22 15:03:24 -04:00
Andreas Olofsson
5bd5d1ff54 Man that's a lot of yak shaving.... 
-added register read/write properly
-removed redundant wrapper layers in maxi/saxi
-changed over to "emesh" interface from packet 103 bit data
-cleaned up maxi
-cleaned up saxi
-removed redundant signals in elink interface (user,lock,..)
-added wrapper to fifo (to carry emesh interface through)

Now comes the fun part of testing
 2015-04-13 23:35:21 -04:00
Andreas Olofsson
baebdab381 Reorganizing files...too many folders after all. 
There is only one elink...
 2015-04-11 00:10:16 -04:00