Andreas Olofsson
b6c95e5b94
Cleanup
2015-11-06 22:34:08 -05:00
Andreas Olofsson
d7bf1389d6
Changing idelay bit map
...
- the 5 bit fields was driving me nuts!
- always work in nibbles, place the msb elsewhere (or work with 16 bit values)
2015-11-03 10:31:06 -05:00
Andreas Olofsson
86e8579e48
Adding testmode for RX
2015-10-07 21:58:50 -04:00
Andreas Olofsson
d7d959da45
Adding software programmable IDELAY
...
- This is DEFINITELY the way to do things, sweep the delays and find the right value. No f'ing way to get these stupid FPGAs to work otherwise with the ridiculuosly over margined PVT nubmers they are running through the STAs. I understand they want to make the design bullet proof, but as a result designers are wasting countless hours overoptimzinng designs and being clever. So much performance is left on the table for expert users.
- Lesson: I/O design should be "self syncrhonizing". Only contraints in the design should be create_clk
- Made RX clock async, too tricky to guarantee that there clock is there. No way to do this if the clock sources are actually independent for RX/TX!
2015-10-07 11:49:46 -04:00
Patrik Lindström
634ff371ac
Bug fixes
2015-06-30 13:32:05 +02:00
Andreas Olofsson
72aff72558
MILESTONE: register read/write working!
...
-Bullet proof clock domain crossings!
2015-05-04 10:49:17 -04:00
Andreas Olofsson
bb8f5f861b
Moving the read response to separate group (not register)
...
Why?
1.) This will allow for support of multiple outstanding channels at some point
2.) Much easier to debug, can tag transactions in test bench
2015-05-04 10:41:42 -04:00
Andreas Olofsson
781121fc61
Cleanup
...
-setting DMA access to zero for now
-taking away wait for elink2 (messes up the access pattern)
-fixing typo in register mape ERX
2015-05-02 23:04:13 -04:00
Andreas Olofsson
23cb2acb31
Updated constants file to fit new register map
2015-05-01 17:52:55 -04:00
Andreas Olofsson
395a1b3cb7
Merge branch 'master' of https://github.com/parallella/oh
...
Adding complete register documentation
Conflicts:
elink/README.md
2015-04-29 11:55:01 -04:00
Andreas Olofsson
3ef05ad63a
Register map twiddling..
2015-04-28 17:00:17 -04:00
Andreas Olofsson
d79447853f
Register name shuffle
2015-04-27 09:28:52 -04:00
Andreas Olofsson
3cb8d1d426
Adding test mode registers for transmit path
...
Makes it possible to easily test the IO path using the mi_ interface
The mi interface is very simple to drive in logic...
2015-04-27 00:04:30 -04:00
Andreas Olofsson
ca835b9607
tweaking register map again...
2015-04-25 23:28:18 -04:00
Andreas Olofsson
919a5fa5e8
Register map twiddles
...
-Fixed test to correspond to new map
2015-04-25 07:09:52 -04:00
Andreas Olofsson
be42ea3b89
Register map change
...
-Changed register map
-Splitting into groups, more natural
2015-04-24 17:38:01 -04:00
Andreas Olofsson
24fc91072d
Adding IDs to keep access signals straight
2015-04-23 23:11:58 -04:00
Andreas Olofsson
842dd60b3e
Adding DMA register to regmap
2015-04-23 18:08:52 -04:00
Andreas Olofsson
4c44c59079
Message box working...
...
-More testing needed!
2015-04-19 21:55:07 -04:00
Andreas Olofsson
00a921b839
Changed register map
...
-Moved "groups" to E,D,C
-Changed names to EL* (shorter is better, clear enough)
-Moved order to fit logical operation during init
-Moved embox registers to MMR group
DONE!
2015-04-18 16:21:45 -04:00
Andreas Olofsson
baebdab381
Reorganizing files...too many folders after all.
...
There is only one elink...
2015-04-11 00:10:16 -04:00
