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Author SHA1 Message Date
aolofsson
f938b7acac Shorter, better names for rams 2022-06-17 23:16:07 -04:00
aolofsson
19074173ff Making stimulus a general purpose test vector engine 
-Should work in an FPGA as well...
-Anything that is synthesizable goes into the hdl/rtl directory...
 2022-06-17 23:04:34 -04:00
aolofsson
996d980059 Adding testbench for stimulus 
-New name, new methodology
 2022-06-17 23:03:32 -04:00
aolofsson
f0d0750dae Adding test template for emesh packet format 2022-06-17 23:01:40 -04:00
aolofsson
1d7dd09b19 Rallying around TARGET for any platform specific RTL 2022-06-17 15:10:19 -04:00
aolofsson
f0372e5afe Adding random pulse generator 2022-06-17 15:10:03 -04:00
aolofsson
d380374049 Adding basic limits to random number generator 2022-06-17 15:09:32 -04:00
aolofsson
70bbde9ccb Adding basic random HW random number generator 
-work in progress...
 2022-06-17 14:40:24 -04:00
aolofsson
a31e16fb25 Increasing timeout value on simctrl to reasonable default 2022-06-17 14:39:23 -04:00
aolofsson
f6610a0f80 Updating emesh monitor 
- Removing hard coded name in file (dumb)
- Adding support for multiple packet sizes
 2022-06-17 12:56:46 -04:00
aolofsson
46310f842e Changing block name to avoid conflict with "soft" constraints 2022-06-12 22:48:14 -04:00
aolofsson
5258c5c357 Adding place holder isolation buffers 2022-05-29 09:21:10 -04:00
aolofsson
e89f815b38 Going back to placing all folders in src 
- Only way to scale, final decision!!
 2022-05-29 08:45:00 -04:00
aolofsson
d8b44971b5 Fixing old WIP typo bug 2022-05-29 08:43:44 -04:00
aolofsson
818ad00d3c Moving mathlib into stdlib 
-Less libraries is better in this case
 2022-05-27 22:01:24 -04:00
Andreas Olofsson
23b26c4a93
Merge pull request #111 from nmoroze/master 
Some tweaks to padring library
 2021-11-26 21:15:20 -05:00
Noah Moroze
a7bae72f34 Pass through tech_cfg_width to iobuf 2021-10-08 18:53:47 +00:00
Noah Moroze
172c1f8732 Make tech_cfg an inout so it can expose tieoffs 2021-10-07 18:32:20 +00:00
aolofsson
24e70f55bd Confusing to have more than one clock for a sync fifo... 2021-09-25 22:35:42 -04:00
aolofsson
5d4ad5b17b Merge branch 'master' of github.com:aolofsson/oh 2021-09-23 09:58:21 -04:00
aolofsson
eb16df1e3c Fixing syntax errors found by surelog 2021-09-23 09:58:08 -04:00
Noah Moroze
eeb0b784c4 Add ring port for tech-specific power-ring signals 2021-08-18 19:31:04 +00:00
Noah Moroze
4942b2509a Fix typo 2021-08-17 19:34:44 +00:00
Andreas Olofsson
e0abb876da
Merge pull request #110 from nmoroze/master 
Add "tech config" pass-through for technology-specific GPIO configuration
 2021-08-15 22:49:09 -04:00
Noah Moroze
b4f1aa3a60 Add generic cell under oh_pads_corner 
To be consistent with how other I/O cells are defined.
 2021-08-13 16:18:37 -04:00
Noah Moroze
3e1d6d8e8d Add parameters to disable POC/cut cells 2021-08-13 16:18:21 -04:00
Noah Moroze
bc9d7f8e55 Insert missing comma 2021-08-07 17:16:40 -04:00
Noah Moroze
d8a28ac153 padring: add pass-through "tech config" for GPIO 
This is an escape hatch for connecting to technology-specific I/O config pins.
 2021-08-05 17:22:47 -04:00
Noah Moroze
adb1bf9eae Fix whitespace in oh_padring 
- Convert tabs to spaces
- Trim trailing whitespace
 2021-08-05 15:48:45 -04:00
aolofsson
88dd3be734 Creating mathlib for arithmetic 2021-08-02 18:18:54 -04:00
aolofsson
4643670a08 Adding ASICLIB description 2021-08-02 18:03:51 -04:00
aolofsson
826bf75d2e Removing depracated script in asiclib 2021-08-02 18:01:55 -04:00
aolofsson
79b1eb5b6c Adding README for asiclib 2021-08-02 18:00:13 -04:00
aolofsson
1fe01b27d2 File cleanup 2021-08-02 17:37:36 -04:00
aolofsson
02ee349faa Adding stdlib (in place of common) 2021-07-29 11:22:25 -04:00
aolofsson
de63dfd907 Major reorg! 
-stdcells moved to asiclib, doesn't make sense to be vectorized
-common is a stupid name, renamed as stdlib
 2021-07-29 11:20:44 -04:00
aolofsson
3cb916f4b5 Fixing typo bug in csa32 2021-07-28 18:27:21 -04:00
aolofsson
aeb391a186 Fixing module name issue 2021-07-28 18:25:24 -04:00
aolofsson
df731e4e13 Adding asiclib scripts directory 2021-07-28 08:48:15 -04:00
aolofsson
9e41b55f22 Adding default property to all cells 
-Can be used to select between different cells (like sizes) that have the exact same logical function
 2021-07-27 22:55:45 -04:00
aolofsson
541ed2fbc8 Fixing csa cell to be single bit 2021-07-27 22:54:00 -04:00
aolofsson
3dbb3755af Adding asiclib 
-Represent set of cells that need hard coded cells or hard coded gate level designs.
 2021-07-27 22:24:40 -04:00
aolofsson
f91d839e11 WIP: Complete refactoring of common lib to support asic cells 
-Changing DW to N for vector width (uniformity, clarity)
-Adding asic cells with SYN statement
-Adding TYPE parameter
-Moving for loops outside of asic gates
-Rename pwr cells to use simpler names
 2021-07-26 22:34:03 -04:00
aolofsson
0a875e193c Removing useless edge detect module 2021-07-26 17:28:52 -04:00
aolofsson
41e5077f06 Removing depracated iobuf cell (now in padring) 2021-07-26 12:02:58 -04:00
aolofsson
50d9ebe637 Implemeting new asic cell approach for latches 2021-07-26 12:01:50 -04:00
aolofsson
f298ded0d0 Removing depracated generic fifo 2021-07-26 11:50:20 -04:00
aolofsson
421fcf6340 Implementign asic cell redirection for clock gates 2021-07-26 11:49:10 -04:00
aolofsson
916d6c8b3d Implementing asic_cell redirection for csa's 2021-07-26 11:46:05 -04:00
aolofsson
15c65d2282 Adding clockmux2 and clockmux4 
-Cover 99% of all cases clock selectors
 2021-07-26 11:44:17 -04:00