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Author SHA1 Message Date
Andreas Olofsson
b1946a7c94 Changed license copyright 
The Parallella Foundation was resolved. Too much of a headache to maintain.  Considering a permanent home in an existing foundation like eclipse, or apache, or other? For now assigning to me. History of code copyright: Adapteva-->Parallella Foundation-->Andreas Olofsson

1.) Most of code developed while Andreas Olofsson was employed at Adapteva

2.) 2016: Adapteva board resolution transfered code to Parallella Foundation under leadership of Andreas Olofsson

3.) 2016: Parallella foundation resolved and code copyright transferred to Andreas Olofsson

None of this should matter given the MIT nature of the license....
 2017-04-01 17:50:04 -04:00
Ola Jeppsson
2f91330d0f common/fpga/create_ip.tcl: Fix error when sub-IP is locked 
- Make local temporary copy
- Don't fail if IP is locked (can happen when partname has changed)

Signed-off-by: Ola Jeppsson <ola@adapteva.com>
 2017-02-10 17:00:55 +01:00
Ola Jeppsson
37a38ab486 zcu102: zcu102: Use Petalinux 2016.4 design as base 
Change partname to:
xczu9eg-ffvb1156-1-i-es2

Don't set BOARD_PART.

Remove si570 pl component.

Full path:
petalinux-bsp/xilinx-zcu102-zu9-es2-rev1.0-2016.4/hardware/xilinx-zcu102-zu9-es2-rev1.0-2016.4/

Signed-off-by: Ola Jeppsson <ola@adapteva.com>
 2017-02-09 23:03:51 +01:00
Ola Jeppsson
02955c09a5 zcu102: zcu102: Define oh_verilog_define 
Define oh_verilog_define to CFG_ASIC=0.

Signed-off-by: Ola Jeppsson <ola@adapteva.com>
 2017-02-07 23:02:10 +01:00
Ola Jeppsson
fbfe55961c fpga/system_build.tcl: Support oh_verilog_define flag 
Workaround for that recent Vivado versions (2016.4) doesn't seem to
support this any longer:
set_property -name {STEPS.SYNTH_DESIGN.ARGS.MORE OPTIONS} -value $foo -objects [get_runs synth_1]

Signed-off-by: Ola Jeppsson <ola@adapteva.com>
 2017-02-07 23:01:50 +01:00
Ola Jeppsson
ee2e234dae Revert "common/hdl: Fix syntax error when CFG_ASIC is undefined" 
This reverts commit 049a031e47ff2dde7bd12b151649350d56fc2e09.
 2017-02-07 19:11:05 +01:00
Ola Jeppsson
afccd4a38b zcu102: zcu102: Fix Makefile deps and clean target 
Signed-off-by: Ola Jeppsson <ola@adapteva.com>
 2017-02-07 18:47:42 +01:00
Ola Jeppsson
8706590599 zcu102: zcu102: Remove cclk1 port 
Fails implementation since it's unconnected but its IO standard is LVDS.

Signed-off-by: Ola Jeppsson <ola@adapteva.com>
 2017-02-07 18:45:52 +01:00
Ola Jeppsson
258cda93d2 fpga/system_build.tcl: Create files for SDK 
Create files needed by Xilinx SDK tool for FSBL generation.

Signed-off-by: Ola Jeppsson <ola@adapteva.com>
 2017-02-07 18:44:04 +01:00
Ola Jeppsson
23c2f8b383 fpga/system_build.tcl: Tweak implementation optimization settings 
This is what ADI HDL uses. I trust that they know what they're doing.

Signed-off-by: Ola Jeppsson <ola@adapteva.com>
 2017-02-07 18:42:20 +01:00
Ola Jeppsson
f7e8ddfe7d fpga/system_build.tcl: Write raw BIN bitstream file 
Write raw BIN bitstream file without metadata, as well as BIT file.

Signed-off-by: Ola Jeppsson <ola@adapteva.com>
 2017-02-07 18:40:01 +01:00
Ola Jeppsson
66d9a97bda fpga/system_build.tcl: Generate timing summaries 
Generate timing summaries for synthesis and implementation.

Signed-off-by: Ola Jeppsson <ola@adapteva.com>
 2017-02-07 18:37:09 +01:00
Ola Jeppsson
b179a70b27 fpga/system_build.tcl: Use $design instead of hardcoded 'system' 
Signed-off-by: Ola Jeppsson <ola@adapteva.com>
 2017-02-07 17:38:41 +01:00
Ola Jeppsson
82cab68bc4 zcu102: zcu102_base: Fix Makefile dependencies and clean target 
Signed-off-by: Ola Jeppsson <ola@adapteva.com>
 2017-02-06 19:45:01 +01:00
Ola Jeppsson
a73f0ae10c zcu102: Synthesize & create bitstream in FPGA project 
Uncomment line.

Signed-off-by: Ola Jeppsson <ola@adapteva.com>
 2017-02-04 21:17:11 +01:00
Ola Jeppsson
d30411c80d elink: Migrate to Ultrascale+ IO primitives 
Breaks zynq.

TODO:
- Should be configurable so we can support both Zynq and zynqplus
  (Ultrascale+).
- Need to add idelay3 register so we can expose entire tap range for
  ultrascale. 9 bits vs 5 bits for zynq.
- IDELAYCTRL fails DRC (Vivado bug?)
- Use .DELAY_FORMAT("TIME") in IDELAYE3.  Depends on IDELAYCTRL.

Signed-off-by: Ola Jeppsson <ola@adapteva.com>
 2017-02-04 21:17:11 +01:00
Ola Jeppsson
bae0889773 zcu102/fpga: Update README 
Signed-off-by: Ola Jeppsson <ola@adapteva.com>
 2017-02-04 21:17:11 +01:00
Ola Jeppsson
346b08382b ip: fifo_async_104x32: Regenerate IP 
Part changed.

Signed-off-by: Ola Jeppsson <ola@adapteva.com>
 2017-02-04 21:17:11 +01:00
Ola Jeppsson
a7aa6ef67f zcu102: Disconnect carrierboard CLKIN_P1 from zcu102_base/cclk 
Fixes synthesis.
zcu102_base/cclk must be tied to *one* package pin.
Need to create a separate clock primitive for CLKIN_P1.
But those pins are for testing, final design should use on-chip
SG-310 oscillator ("REFA").

Signed-off-by: Ola Jeppsson <ola@adapteva.com>
 2017-02-04 21:17:02 +01:00
Ola Jeppsson
c172977c00 zcu102: hdl: Change IOSTD_ELINK to 1.8v LVDS 
Signed-off-by: Ola Jeppsson <ola@adapteva.com>
 2017-02-04 18:03:56 +01:00
Ola Jeppsson
bf24d4e491 zcu102: Set board part to zcu102 in zcu102_base ip and zcu102 project 
Seems the right FPGA model is:
xczu9eg-ffvb1156-2-i-es2

No way to tell for sure (JTAG doesn't give exact model) without removing
heatsink from board :(
Should be same package pins though.

Signed-off-by: Ola Jeppsson <ola@adapteva.com>
 2017-02-04 17:59:50 +01:00
Ola Jeppsson
214278ea0b common/fpga/system_init.tcl: Support board_part variable 
Signed-off-by: Ola Jeppsson <ola@adapteva.com>
 2017-02-04 17:56:43 +01:00
Ola Jeppsson
74eb5be55b zcu102: Add some documentation 
- Carrier board FMC pinout.
- ZCU102 master XDC file.

Signed-off-by: Ola Jeppsson <ola@adapteva.com>
 2017-02-04 17:54:58 +01:00
Ola Jeppsson
d7fee44574 zcu102: Fix constraints 
- Some pin mappings were wrong (don't code when tired).
- Use 1.8v IO standards.

Signed-off-by: Ola Jeppsson <ola@adapteva.com>
 2017-02-04 17:52:12 +01:00
Ola Jeppsson
06e80284b2 zcu102: Add constraints for SI570 video clock 
Signed-off-by: Ola Jeppsson <ola@adapteva.com>
 2017-02-04 17:51:42 +01:00
Ola Jeppsson
049a031e47 common/hdl: Fix syntax error when CFG_ASIC is undefined 
Workaround for:
Recent Vivado (2016.4) synth step seems to have dropped support for
"-verilog_define CFG_ASIC=0"

Signed-off-by: Ola Jeppsson <ola@adapteva.com>
 2017-02-03 02:26:37 +01:00
Ola Jeppsson
6a50842b46 zcu102: Update block design 
Ports:
Remove HDMI ports.
Remove cclk0 port.
Add cclk0_[pn] (tile 0-7) ports.
Add cclk1_[pn] (tile 8-15) port.
Add clkpd_1p8v port.

Nets:
Connect zcu102_base/cclk to cclk0 and cclk1.
Connect clkpd_1p8v to zcu102_base_0/chip_nreset.

Signed-off-by: Ola Jeppsson <ola@adapteva.com>
 2017-02-03 00:53:47 +01:00
Ola Jeppsson
094f417f66 zcu102: Add package pins for FMC0 connector 
Signed-off-by: Ola Jeppsson <ola@adapteva.com>
 2017-02-03 00:47:18 +01:00
Ola Jeppsson
bac760678c Add zcu102 design 
Work in progress.
Design looks good.
Need to add pin and timing constraints.

Signed-off-by: Ola Jeppsson <ola@adapteva.com>
 2017-02-01 11:11:37 +01:00
Ola Jeppsson
440005fbc0 common/fpga/create_ip.tcl: Add Ultrascale+ to supported families 
Signed-off-by: Ola Jeppsson <ola@adapteva.com>
 2017-01-31 18:49:12 +01:00
Ola Jeppsson
12e7b5ad14 ip: fifo_async_104x32: Switch to ultrascale device 
Signed-off-by: Ola Jeppsson <ola@adapteva.com>
 2017-01-31 18:42:47 +01:00
Ola Jeppsson
83a37d2469 ip: fifo_async_104x32: Update to Vivado 2016.4 
Signed-off-by: Ola Jeppsson <ola@adapteva.com>
 2017-01-31 13:42:59 +01:00
Raphael Nestler
1916ab8777 docs: Fix GPIO description 2017-01-26 10:52:56 +01:00
Andreas Olofsson
e7abddbcb5 Adding planning document for boards 
-Not CAD accurate, only for visual planning
 2016-12-21 12:05:37 -05:00
Andreas Olofsson
b350deb827 Adding directory of standards 
-Summary
 2016-11-15 06:51:39 -05:00
Andreas Olofsson
d1f9bdffbb Adding place holder definition for open source 2016-10-24 11:24:08 -04:00
Andreas Olofsson
63f77ef832 Format change for board record 
- explicit link
- adding docs
 2016-10-24 11:17:45 -04:00
Andreas Olofsson
8e195c4d17 Cleanup 2016-10-24 10:57:24 -04:00
Andreas Olofsson
6546787c77 Adding Rascal board 2016-10-24 10:52:24 -04:00
Andreas Olofsson
e7745a3bec Link cleanup 2016-10-24 10:33:30 -04:00
Andreas Olofsson
3ac57dabba Adding open source board resource 2016-10-24 10:27:58 -04:00
Andreas Olofsson
383cda2550 Adding preliminary r5 opcodes 2016-09-26 15:16:00 -04:00
Andreas Olofsson
5a583c598c Adding buffer 
- Sometimes you need to instatiate buffers manually in RTL to get around some absolutely braindead behaviour in eda tools. Not often, but sometimes...
 2016-09-03 14:59:30 -04:00
Andreas Olofsson
70533b57b0 Refactoring asic code 
- remove redundant hierarchy
- using shorter/better names to make sdc constraints less ugly
 2016-09-03 14:40:51 -04:00
Andreas Olofsson
94469ed5f4 Resetting shift register 
- Less red to look at...
 2016-09-03 14:40:21 -04:00
Andreas Olofsson
a306aa5178 Removing one level on redirection on clockor 
- It was getting annoying....
 2016-09-02 00:39:32 -04:00
Andreas Olofsson
128c4015b3 Adding reset to wakeup pipeline 
- Suspect behaviour when clock is absent..
 2016-09-01 19:32:48 -04:00
Andreas Olofsson
0f8beea513 Fixing reset bug for MIO emode 
- Shows up when there is no free running clock. Don't assume there is a clock at startup!
 2016-08-28 19:14:45 -04:00
Andreas Olofsson
3e18d921d6 Adding DV hook into SPI block 
- Inputting large amount of data through SPI in DV is soooo painfully slow. Added hook to speed up development. 100x speedup in verification time-->100x speed up in design team.
 2016-08-26 23:50:05 -04:00
Andreas Olofsson
dc22df0d5c Fixing MIO synthesis errors/warnings 2016-08-26 00:41:42 -04:00