Andreas Olofsson
fa374e666a
Cleanup
2015-05-09 08:57:49 -04:00
Andreas Olofsson
eb3051ea93
Cleaning up logic to fit new access/packet interface
...
(pre-debug)
2015-05-09 08:56:51 -04:00
Andreas Olofsson
ab26378a99
Adding elink with axi interfaces
2015-05-09 08:52:55 -04:00
Andreas Olofsson
d83efbdb8e
Cleaning up initial constraints
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-Now generates bit stream
-It won't work, but it's a start...
2015-05-08 20:56:33 -04:00
Andreas Olofsson
a52fa86edb
Fixing instances errors from fpga synthesis
2015-05-08 20:55:31 -04:00
Andreas Olofsson
9793be3bf0
Fixing crucial error in documentation
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-Nothing worse than incorrect comments!
2015-05-07 23:52:02 -04:00
Andreas Olofsson
b2b7f96e86
Making FIFO/memories easier to use
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-WIDTH/DEPTH parameters
-Removing references to "clean" in ifdefs
2015-05-07 23:50:34 -04:00
Andreas Olofsson
dc8cb83268
Cleanup
2015-05-07 23:49:50 -04:00
Andreas Olofsson
4f3f9b9de5
Fixing bug in clock frequency parameter
2015-05-07 23:49:07 -04:00
Andreas Olofsson
38d7fe1af9
Clock cleanup
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-Moving to single clock
-Unifying the timescale (1ns period)
-Stopping access when done with stimulus file
2015-05-07 23:46:32 -04:00
Andreas Olofsson
1f6c18a764
Using fifo_cdc instead of fifo_async
2015-05-07 23:45:36 -04:00
Andreas Olofsson
c51f8f3dc9
Adding clock buffer
2015-05-07 23:44:39 -04:00
Andreas Olofsson
773bab5c6a
First version of synthesis tcl scripts for elink example
2015-05-07 23:43:05 -04:00
Andreas Olofsson
1d5b967a7f
Adding simulation model for PLL
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NOTE: Depends on CLKIN machting parameter in model!
For example, if clkin=100MHZ, period parameter must be 10
2015-05-06 12:28:25 -04:00
Andreas Olofsson
bba7511f15
Fixing syntax errors caught in synthesis
2015-05-06 12:27:13 -04:00
Andreas Olofsson
61de7c366a
Cleaning up clock divider
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-moving 90 degree phase shift to PLL
2015-05-06 12:26:07 -04:00
Andreas Olofsson
ba32323306
Cleaning up clocks
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-moving to "real" Xilinx PLL instantiation
-one PLL for CCLK one for LCLK
-removing clock dividers, can't work at speed, put inside model
-configuration needs to be done differently
-removing pll_bypass signal, can't work with logic
-clocks should be done with hard macro primitives (no logic)
2015-05-06 12:23:15 -04:00
Andreas Olofsson
4f487d498e
Making simulation more "real"
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-Working with timescale (for viewer mostly)
-Now using TARGET_XILINX as default in sim
2015-05-06 12:21:39 -04:00
Andreas Olofsson
a36875ac09
Adding basic emehs transaction generator
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-Replace with DMA...
2015-05-05 21:39:20 -04:00
Andreas Olofsson
d8b5fa78ef
Adding emesh as basic building block
2015-05-05 21:38:41 -04:00
Andreas Olofsson
d0439f871f
Adding example design for FPGA
2015-05-05 21:37:17 -04:00
Andreas Olofsson
c843fc5fe0
Renaming for my sanity (etx/erx split)
2015-05-05 14:56:35 -04:00
Andreas Olofsson
300e5a14fc
Reorg
2015-05-05 14:47:21 -04:00
Andreas Olofsson
a3cfa17b06
Removing old module
2015-05-04 22:38:28 -04:00
Andreas Olofsson
3e74d68dcc
Both input and output models were wrong.
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Should match datasheet now...
2015-05-04 22:35:55 -04:00
Andreas Olofsson
de74f8accc
Removed synchronizer, not needed
2015-05-04 22:34:14 -04:00
Andreas Olofsson
b2846c5312
MILESTONE: Read/write works back and forth
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-Pipeline looks good, now need to test clk1>>clk2 and clk2>clk1
-Still not completely happy with reset (using async for now)
2015-05-04 17:13:51 -04:00
Andreas Olofsson
570fbffd7f
Baking in the IO wait signal into rd/wr wait
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-Separate waits for rd/wr wait
-Adding wait to protocol block as well
-io_wait always goes through
-using active frame signal to select/clear data for output
2015-05-04 17:10:32 -04:00
Andreas Olofsson
dcf72537e4
Separate rd/wr stalls
2015-05-04 17:09:50 -04:00
Andreas Olofsson
c3fe37dc90
Separating rd/wr wait for pipeline stall
2015-05-04 17:09:23 -04:00
Andreas Olofsson
ec3dbc910a
Using async reste on fifo output access signal
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-For cases where there is no clock at output
2015-05-04 17:07:55 -04:00
Andreas Olofsson
0aba754b7e
Cleanup
2015-05-04 10:54:42 -04:00
Andreas Olofsson
8b37d29f27
File cleanup
2015-05-04 10:54:23 -04:00
Andreas Olofsson
72aff72558
MILESTONE: register read/write working!
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-Bullet proof clock domain crossings!
2015-05-04 10:49:17 -04:00
Andreas Olofsson
bb8f5f861b
Moving the read response to separate group (not register)
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Why?
1.) This will allow for support of multiple outstanding channels at some point
2.) Much easier to debug, can tag transactions in test bench
2015-05-04 10:41:42 -04:00
Andreas Olofsson
e9d6794833
Blocking TX outgoing transcations on LINKID match
2015-05-04 10:41:14 -04:00
Andreas Olofsson
25b0b188ff
Implementing register readback on read response channel
2015-05-04 10:40:43 -04:00
Andreas Olofsson
6907d39490
Making readback work
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-Simplifying logic for rx_en
-Reaback data was incorrectly pipelined (one too many)
2015-05-04 10:39:01 -04:00
Andreas Olofsson
b63de8b1d8
Filter the txwr access
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We don't want reset/clock transaction to propagate through etx!
2015-05-04 10:37:27 -04:00
Andreas Olofsson
75f653ffd6
Naming cleanup
2015-05-04 10:37:08 -04:00
Andreas Olofsson
b375aaeb07
Adding back emesh access
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-Write from emesh, read from mi.
-Final decision?
-Make readback 64 bits.
2015-05-04 10:36:07 -04:00
Andreas Olofsson
861c690ebb
Adding rd_en to fifo_async
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-Need to hold output when there is no read_access
(important assumption!)
2015-05-04 10:35:23 -04:00
Andreas Olofsson
1ee720fc67
Organization changes
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-dma with packet format
-using the fifo_cdc block
2015-05-03 23:29:32 -04:00
Andreas Olofsson
51b14f41ce
wait in vs. wait out confusion
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wait_out is the signal being driven out telling someone else to wait
wait_in is the incoming signal telling "you" to wait".
2015-05-03 23:26:43 -04:00
Andreas Olofsson
cfe811e7a7
Complete redesign
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-Following access,wait, packet pipeline format
-Use a priority arbiter
2015-05-03 23:25:19 -04:00
Andreas Olofsson
5470c1dc8f
Enable 2 clock operation for EMMU
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The dual port memory should support this in most cases
2015-05-03 23:24:27 -04:00
Andreas Olofsson
47a143eada
Turning on clocks by default (low frequency)
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Seems safer
2015-05-03 23:23:28 -04:00
Andreas Olofsson
2d698266de
Making dma quiet until implemented
2015-05-03 23:23:02 -04:00
Andreas Olofsson
b05f236d13
Clocks on during reset
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-Otherwise we can't do sync reset anywhere
-glitch on exit from reset? Do we care? Everything is static
-Need to check this again!
2015-05-03 23:21:10 -04:00
Andreas Olofsson
21dcedbda2
Adding simple priority arbiter
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Yes it's simple, but youl should never have to rewrite this code
For larger arbiters, too much risk of making a mistake...
Arbitration mistakes aver nasty to find and nasty to debug!
2015-05-03 23:19:40 -04:00
