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Author SHA1 Message Date
Andreas Olofsson
19e22c38d7 Adding proper wait to fifo_cdc 
If there is a waitm, we should
1.) Not increment the read pointer
2.) Hold the packet steady until wait signal goes away
3.) Hold access high, keep request intact
 2015-05-03 23:17:23 -04:00
Andreas Olofsson
781121fc61 Cleanup 
-setting DMA access to zero for now
-taking away wait for elink2 (messes up the access pattern)
-fixing typo in register mape ERX
 2015-05-02 23:04:13 -04:00
Andreas Olofsson
2da588721a Fixed verilog syntax issue 
-Not sure what parameter couldn't be used directly here?
-Works fine when parameter is assigned to wire.
 2015-05-02 23:03:14 -04:00
Andreas Olofsson
dcd2d0b111 Clock/reset fixes 
-Making reset async
-lclk_div4 always on (makes reset safer, not a big loss)
-filtering non-matching transactions
 2015-05-02 22:42:33 -04:00
Andreas Olofsson
cb9a1f50dd Fixing ecfg_clocks 
-Was missing clock connection
-Adding ID to match only to the right transcations
 2015-05-02 22:40:27 -04:00
Andreas Olofsson
ebd9a89afd Adding constants to handle model 2015-05-02 21:30:26 -04:00
Andreas Olofsson
56fa70c0dd Connecting wait output from e16_model 2015-05-02 21:29:43 -04:00
Andreas Olofsson
130caa64b6 E16 model cleanup 
-fixing false error message
-removed emesh_interface isntance (not needed..)
-set floating inputs to zero
 2015-05-02 21:28:09 -04:00
Andreas Olofsson
e5fc895a25 Cleanup 2015-05-01 18:33:29 -04:00
Andreas Olofsson
340d99cab1 Instance renaming 
Will help with FPGA synthesis reports (uniqueness needed sometimes)
 2015-05-01 18:19:36 -04:00
Andreas Olofsson
8461277ab1 Complete redesign of configuration register file 
-There is now only one clock domain crossing involved with the reg files/ All clock domain crossings use the same 104 bit wide async fifo! If it's broken we are screwed, if it works we are perfect!
-Configuration can be done from host through txwr/txrd path of any register
-The RX IO pins can only access the RX side of the design
 2015-05-01 17:58:16 -04:00
Andreas Olofsson
f215e07ce9 Updated to fit new ERX_RR register 
-Read response now returns to a memory mapped register
 2015-05-01 17:53:55 -04:00
Andreas Olofsson
23cb2acb31 Updated constants file to fit new register map 2015-05-01 17:52:55 -04:00
Andreas Olofsson
4059a6eaa2 Created unified one clock modular confi for RX/TX 
-Solves clock domain crossing uglyness
-Very nice and clean!!
-Only compromise is that the RESET and CLOCK registers aren't readable
 2015-05-01 17:51:12 -04:00
Andreas Olofsson
20534a6ed1 Added testmode to transmitter 
-pin driven testmode driven..b/c fpga designers often don't like software
-and because it's really convenient, press a push button and see a pattern appear
-removed protocol description, goes in README.md, there should only be one source for documentation
-shortened signal names for ecfg
-changed to "clk" input now that everything is single clock
 2015-05-01 17:47:24 -04:00
Andreas Olofsson
93f0fb6220 README cleanup 2015-05-01 17:42:12 -04:00
Andreas Olofsson
1c14ccd5d9 Generalizing emailbox 
-There should be two clocks
(even though there is only one clock in erx)
 2015-05-01 17:34:04 -04:00
Andreas Olofsson
08b871941d Adding e16 elink golden reference to dv environment 2015-05-01 17:32:52 -04:00
Andreas Olofsson
0ca303432b Cleanup 2015-05-01 17:31:45 -04:00
Andreas Olofsson
0cc00dcd2e Changed DMA interface to "packet style" 
-Packet format is really compact, a huge deal after all..
-Also commenting out content for now
 2015-05-01 17:30:08 -04:00
Andreas Olofsson
800dacdff4 Updated register map and interface 
-Changed DMA descriptor locations
-Changed colid/rowid -->chipd[11:0] (more consistant)
-Added access column (R/W)
 2015-05-01 17:27:24 -04:00
Andreas Olofsson
e168bd5f98 reorg 2015-05-01 17:21:45 -04:00
Andreas Olofsson
0762b90fef Reorg 2015-05-01 17:21:21 -04:00
Andreas Olofsson
d541a261a6 Adding Epiphany16 elink RTL implementation as reference 
This is pretty big, wonder if anybody will notice?

Why am I doing this?

Because the elink has been haunting us for years. This way we will finally have a "golden reference" simulator model for those who insist on designing their own elink protocol (aginst my recommendation). This is equivalent to having a "bfm-bus functional model" for AXI. The spec is nice, but it's always up for interpretation. We have had some issues with documenting the protocol corretly. While we will fix the documentation, please note that the source code and design verification environment will always be the golden version. This is after all "the silicon".

For me and everyone else, it becomes part of the open source design verification environment to test the elink.

Enjoy....
 2015-05-01 17:14:50 -04:00
Andreas Olofsson
a58c2d5279 Adding clock domain crossing module for emesh 
-Generic, built for reuse
 2015-05-01 17:13:44 -04:00
Andreas Olofsson
754aae749f Adding various helper modules 2015-05-01 17:13:21 -04:00
Andreas Olofsson
5f15ed220d Changing name 2015-05-01 14:42:15 -04:00
Andreas Olofsson
ad401d09e0 ?? 2015-04-30 23:35:01 -04:00
Andreas Olofsson
49bcc348e4 Making register map look more like Epiphany 2015-04-30 23:33:00 -04:00
Andreas Olofsson
395a1b3cb7 Merge branch 'master' of https://github.com/parallella/oh 
Adding complete register documentation

Conflicts:
	elink/README.md
 2015-04-29 11:55:01 -04:00
Andreas Olofsson
2ee3c7d942 merging local readme 2015-04-29 09:27:15 -04:00
Andreas Olofsson
861f5818d2 Updated with new registers and protocol 2015-04-29 09:24:47 -04:00
Andreas Olofsson
3ef05ad63a Register map twiddling.. 2015-04-28 17:00:17 -04:00
Andreas Olofsson
d00d58d116 Read response now a readable memory mapped register 
Much better...hidden addresses SUCK!
 2015-04-28 16:58:45 -04:00
Andreas Olofsson
2460aa9247 Bypass erx remap on all ID matches 
Not just for read responses..
 2015-04-28 16:58:05 -04:00
Andreas Olofsson
a6ac9b4666 Added bit to etx_remap 
-To enable writing to ERX, we need to include the group number
-support groups F,E,D,C (bits [19:18])
 2015-04-28 16:56:31 -04:00
Andreas Olofsson
4ae2c1ecbf MILESTONE! Working test with new memory map and 2 link system 2015-04-28 16:55:57 -04:00
Andreas Olofsson
6b2d479692 DV environment cleanup 
-removed floating signals
-blocking ID transactions from reaching memory  (should be done in real design as well)
 2015-04-28 16:55:12 -04:00
Andreas Olofsson
22bf7a6b0e Adding stride to EDMA 
-Still need some time to think through this..wip
 2015-04-28 16:54:09 -04:00
Andreas Olofsson
a2ceb8ff6e Cleanup, two-link environment working 
-Write to config registers from RX path now working
 2015-04-28 00:47:26 -04:00
Andreas Olofsson
02812c03a8 Fixing bug on 64 bit register write 2015-04-28 00:46:40 -04:00
Andreas Olofsson
67a05c9363 Fixing floating wait signal bug 2015-04-28 00:46:03 -04:00
Andreas Olofsson
0431d79992 Enabling RX always 
-Should we ever turn this off?
 2015-04-28 00:45:16 -04:00
Andreas Olofsson
96c35c4908 Removing filter for rxwr_access 
-Needed to enable simple mi_write interface on RX
 2015-04-28 00:44:20 -04:00
Andreas Olofsson
f544c44a08 Adding register access from RX 
-Access without symmetry was awkward, now we can reach regs from TX or RX side
-Removes a special path for mailbox (came for free)
-At the same time reduced clock complexity (one clock for system!!)
-Moved mailbox to top level
-Changed main clock to "sys_clk" for all
 2015-04-27 23:51:00 -04:00
Andreas Olofsson
e1a295998f Adding 2nd elink to dv env 
-The single link env wasn't giving enough coverage
-This is also preparing for inserting the chip reference model...
 2015-04-27 23:45:43 -04:00
Andreas Olofsson
6b108f5e1f Adding reset to synchronizer 
(cause there may not be a clock...)
 2015-04-27 16:03:57 -04:00
Andreas Olofsson
df53a2dc4f Adding missing reset 2015-04-27 16:03:12 -04:00
Andreas Olofsson
a1722b7ae6 Adding timeout circuit 2015-04-27 16:02:15 -04:00
Andreas Olofsson
c9124f415b Added "timeout" to elink interface 
-Use as error interrupt?
-Is there another method for checking error?
 2015-04-27 15:11:56 -04:00