Andreas Olofsson
a44778b8be
Putting all ip generator blocks in one repo
2015-11-13 16:21:53 -05:00
Andreas Olofsson
24afa3c9a0
Deleting old files
2015-11-12 11:00:23 -05:00
Andreas Olofsson
3f1296b099
Cleanup
2015-11-12 10:50:05 -05:00
Andreas Olofsson
9ada08a42c
Adding parallella.bit.bin
2015-11-11 14:28:38 -05:00
Andreas Olofsson
038d39def7
Defparam typo
...
- Not caught by iverilog!! (file bug??)
- Caught by Vivado.
2015-11-11 14:13:38 -05:00
Andreas Olofsson
0a2ea66b7e
Bug fix. Adding missing ID parameter.
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- would only show up at different ID
- better to always make defauly nonsense
- sneaky...
2015-11-11 13:58:04 -05:00
Andreas Olofsson
3f0efb9db2
Adding dummy.elf for bootgen
2015-11-11 13:56:48 -05:00
Andreas Olofsson
464700c0b9
Adding converter script for bootgen
2015-11-11 13:56:09 -05:00
Andreas Olofsson
bb084f1670
Adding skeleton for adi sdr design
...
Now need to integrate elink in this
2015-11-11 00:42:14 -05:00
Andreas Olofsson
62305244e9
Build script fixup + gitignore
...
- Filtering "src" wasn't such a good idea...
- Fixing script for bitstream, bootgen doesn't overwrite existing bit stream files (thanks Xilinx, cost me an hour of anxiety!!)
2015-11-11 00:29:15 -05:00
Andreas Olofsson
61eb56c6f7
Final Vivado fixups:
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- reduced frame fanout, removed clock gater in erx_io (improves speed path)
- driving constants on "wid signals" (proper)
- making lock signal 1 bit wide to remove warning
- moved backed to BUFIO for IDDR blocks
2015-11-09 16:09:12 -05:00
Andreas Olofsson
c84e1c96b7
Adding hdmi pins for parallella
2015-11-09 13:22:08 -05:00
Andreas Olofsson
01fd24e069
Fixing synchronization reset speed path
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- This seems silly, why even have a syncrhonizer
- Safe to set speed path?
2015-11-09 00:16:35 -05:00
Andreas Olofsson
405c322d75
Adding build shell script for headless
2015-11-08 07:33:16 -05:00
Andreas Olofsson
9383f32764
Making sure ETYPE is set to 0.
2015-11-06 22:41:43 -05:00
Andreas Olofsson
aa940c2a39
Fixing typos
2015-11-06 22:40:59 -05:00
Andreas Olofsson
8b3fa77df1
Added missing index
2015-11-06 20:47:16 -05:00
Andreas Olofsson
1fa3543ba1
Changing back to lower cases, works..
2015-11-06 20:46:41 -05:00
Andreas Olofsson
6e2ee17481
Updated system memory map
2015-11-06 20:44:18 -05:00
Andreas Olofsson
c9dc9c33ee
Almost done connecting
...
- AXI connections not working properly...
2015-11-06 18:26:09 -05:00
Andreas Olofsson
63bf5d25a4
Moving to active low reset
...
- Because this is the right thing to do for chips
- Not going to tell you why...
2015-11-06 16:51:57 -05:00
Andreas Olofsson
8a89b7e185
Adding more structured vivado build files
2015-11-06 14:11:46 -05:00
Andreas Olofsson
84b5af5b3a
Cleanup
2015-11-06 14:10:35 -05:00
Andreas Olofsson
3969e6d19e
Moving to MIT license
2015-11-06 11:25:05 -05:00
Andreas Olofsson
8b2974feae
Massive reorg!
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- flattening hierarchy
- removing junk
2015-11-06 10:59:22 -05:00
Andreas Olofsson
0fcea92b0d
Scripts per "project"
2015-11-06 06:58:47 -05:00
Andreas Olofsson
90998b8ad0
Adding parallella synthesis scripts
2015-11-06 06:58:14 -05:00
Andreas Olofsson
6cb5f88073
Moving block deisgns into a single Parallella module
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- Easier to maintain
- Better sandbox
2015-11-06 06:56:56 -05:00
Andreas Olofsson
bc53400888
Adding parallella block design
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-Start with gui
-Generate block design
-Edit text, this is f'ing crazy!
-If this is the only way to use the vivado IP not sure I want it
-Strive towards doing everything in verilog
-Split into:
1.) Verilog block (no IP!)
2.) One top level to instantiate IP + clean verilog block
-Never fight the tools..
2015-05-22 21:38:39 -04:00
