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Author SHA1 Message Date
Andreas Olofsson
7f0491d206 Cleaning up GPIO 
- AW parameter was missing in p2e
- Blocking input data with input enable (alsom done at io pad)
 2016-03-21 11:20:59 -04:00
Andreas Olofsson
93154c38f8 Adding special div2 logic for clock divider 
- Using negedge of clock for phase shifting 2nd clock by 90 degrees. Used by elink and mio
 2016-03-21 11:19:25 -04:00
Andreas Olofsson
3fa5fce86f Cleaning up fifos 
- Making default parameter generic (will need to fix elink next..)
- Brining out fifo status for cdc module, goes to status registers (very useful for debugging)
 2016-03-21 11:18:07 -04:00
Andreas Olofsson
b61d55533e Fixing par2ser bugs 
-access out signal was broken (may need to fix again for spi)
-lsbfirst mode was broken
-made datasize 8 bits at interface
 2016-03-21 11:16:42 -04:00
Andreas Olofsson
490a3f6be1 SPI compilation cleanup 
- due to changes in par2ser and clock divider
- disadvantage of using common modules that change...
 2016-03-21 11:15:41 -04:00
Andreas Olofsson
fec6a98d90 Refactoring mio 
- changing datapath name to mio_dp (new methodology)
- top level should be complete block (with control + clock) for ease uf use
- clock renaming
 2016-03-21 06:15:50 -04:00
Andreas Olofsson
5b799de0eb Augmenting dv for mio 
- now includes mio regs as well
- next: create a complete block, ie dog fooding to include the mio_regs an axi interface, and a decoder interface to make it look like a subsystem (like the elink)
 2016-03-20 22:40:36 -04:00
Andreas Olofsson
5edf209983 New MIO integration 
- removing tx protocol block (reduces to par2ser)
- adding status bits to interface
- adding control signals from mio_regs
 2016-03-20 22:39:22 -04:00
Andreas Olofsson
5ff50f78c0 Fixing mtx io logic 
- adding support for single data rate
- removing wait logic from io registers, should only go to fifo
 2016-03-20 22:37:50 -04:00
Andreas Olofsson
d800325f50 Reformatting to use "N" as the main parameters 
-simpler..
 2016-03-20 22:37:30 -04:00
Andreas Olofsson
308b46366a Refactoring rx to use ser2par block 2016-03-20 22:36:33 -04:00
Andreas Olofsson
c18177c8a7 Adding register 
- These can be used to make the configuration of the mio datapath programmable
- This is what I should have done for the elink. Always separate the control from the datapath!!
 2016-03-20 22:35:43 -04:00
Andreas Olofsson
f6f1009b52 Removing protocol block, redundant 2016-03-20 22:35:30 -04:00
Andreas Olofsson
d1fd144374 New and improved MIO interface 2016-03-20 22:33:57 -04:00
Andreas Olofsson
e5a8227509 Adding features to clock divider 
-splitting out period from phase
-adding a second phase shifted clock (running off one counter)
-adding orthogonal control of rising and falling edge
 2016-03-20 18:17:26 -04:00
Andreas Olofsson
015b969ac2 Making default parameter N=1 for muxes 
- Less reconfiguring of parameters at instantiation time
 2016-03-17 23:41:56 -04:00
Andreas Olofsson
e36a817846 Fixing link script 2016-03-13 09:31:45 -04:00
Andreas Olofsson
4b1372eb3b Implementing GPIO readback circuit 
-added test, looks good
-reduced decoder width to 16 regs (seems reasonable for gpio)
 2016-03-13 09:28:17 -04:00
Andreas Olofsson
4517280e45 Adding emesh readback circuit 2016-03-13 09:27:39 -04:00
Andreas Olofsson
a8182de5e1 Adding environment setup script 2016-03-12 16:49:56 -05:00
Andreas Olofsson
4d172960c1 Renaming the generic dut template file 2016-03-11 16:40:30 -05:00
Andreas Olofsson
e1f8b1d6c4 Adding dummy dut to make autocomplete work in emacs 2016-03-11 16:38:17 -05:00
Andreas Olofsson
74d1a9dc72 Fixing SPI header file inclusion issue 2016-03-11 15:08:01 -05:00
Ola Jeppsson
a6aba4cd1f parallella/fpga/headless_e16_z70{1,2}0: Fix Makefile clean target 
Update for output file name change

Signed-off-by: Ola Jeppsson <ola@adapteva.com>
 2016-03-11 17:06:25 +01:00
Ola Jeppsson
fc9a8fc331 parallella/fpga/Makefile: Update for name changes 
Signed-off-by: Ola Jeppsson <ola@adapteva.com>
 2016-03-11 16:31:18 +01:00
Ola Jeppsson
f7edd3cb37 parallella/fpga: Add headless e16 z7010 project 
Copy of z7020 project.
Small changes, 99% could be reused.

Diff vs. z7020 in:
parallella/fpga/headless_e16_z7010-vs-z7020.diff

Compiles but NOT TESTED.

Signed-off-by: Ola Jeppsson <ola@adapteva.com>
 2016-03-11 16:31:18 +01:00
Ola Jeppsson
3cd1cec020 parallella/fpga/headless_e16_z7020: Explicitly set number of GPIOs 
For consistence w/ z7010 project.

Signed-off-by: Ola Jeppsson <ola@adapteva.com>
 2016-03-11 16:31:18 +01:00
Ola Jeppsson
755904486e parallella/fpga: Rename headless to headless_e16_z7020 
Modify build script to output:
parallella_e16_headless_gpiose_7020.bit.bin

This is the same naming convention used by the old elink code.

Signed-off-by: Ola Jeppsson <ola@adapteva.com>
 2016-03-11 16:31:18 +01:00
Ola Jeppsson
4b943fc169 parallella/hdl/parallella_base:pgpio: Inherit NGPIO 
Inherit NGPIO from parallella_base.

Signed-off-by: Ola Jeppsson <ola@adapteva.com>
 2016-03-11 16:23:46 +01:00
Andreas Olofsson
56ed1626b5 SPI working! 
-changed register file sampling to falling edge of sclk...ran out of edges
-fixed the register map for readback
-fixed status register
-fixed user register decode
 2016-03-10 22:04:24 -05:00
Andreas Olofsson
871da0488e Completed readback circuit on master 2016-03-10 22:03:38 -05:00
Andreas Olofsson
b34a3795e8 Completed basic SPI test 
- configure master
- write to tx fifo
- read from remote slave
- read from local master register
 2016-03-10 22:02:25 -05:00
Andreas Olofsson
a7003be8e9 Changing SPI command structure 
- Read/write commands should be at MSBs (7:6)
- Fixed fifo read race..need to look at this again
 2016-03-10 17:33:52 -05:00
Andreas Olofsson
3ca89dca2b Fixed serializer bug 
- ..hopefully last one
- incorrect stall signal made transactions get lost
 2016-03-10 17:33:02 -05:00
Andreas Olofsson
ed8d29ee2c Fixing serializer bug 
- SPI now working...
 2016-03-10 17:03:38 -05:00
Andreas Olofsson
da6856befa Adding reset signal to pulse interfaces 
- Needed for some logic with feedback, otherwise you get "x" loop
- Those who don't need it should be able to connect nrest to 1'b1
 2016-03-10 17:02:03 -05:00
Andreas Olofsson
286914e53c SPI debug cleanup 2016-03-10 17:01:29 -05:00
Andreas Olofsson
534fa69b50 Fixing SPI slave write register bug 
- Writes working
 2016-03-10 17:00:52 -05:00
Andreas Olofsson
f9414d91ee Changin SPI slave parameter 
- More natural to work with UREGS
 2016-03-10 17:00:13 -05:00
Andreas Olofsson
af96108db1 Fixing SPI bugs 
- Now working with byte addresses
- Wait should be on prog_full
 2016-03-10 16:58:18 -05:00
Andreas Olofsson
4589062821 Fixing SPI pushback contention bug (typo) 2016-03-10 16:57:37 -05:00
Andreas Olofsson
383dd50b99 Fixed lethal off by one fifo full bug! 2016-03-10 14:58:29 -05:00
Andreas Olofsson
63b56d9ec9 Adding command reg to spi master 
- Makes the emode more efficient, only setup command once
 2016-03-10 14:20:25 -05:00
Andreas Olofsson
8cf7c40c44 Simplifying spi slave 
- Clock sync made easier by detecting rising edge of ss
- Piping data into slave regs
- State machine simplified
 2016-03-10 14:19:07 -05:00
Andreas Olofsson
d57306619b Adding SPI documentation 2016-03-10 14:17:50 -05:00
Andreas Olofsson
6ad31e5c20 Cleanup GPIO docs table 2016-03-10 14:17:33 -05:00
Andreas Olofsson
e08f5a8fc7 Adding address table to GPIO 2016-03-10 11:13:24 -05:00
Andreas Olofsson
41e789b677 Refactoring to maximize code reuse 
-using common clock divider, ser2par block
-starting the readbkack circuit + auto transfer
 2016-03-10 11:07:51 -05:00
Andreas Olofsson
a5b4768b3b Vectorizing edge2pulse module 2016-03-10 11:07:14 -05:00
Andreas Olofsson
e900ecca2a Simplifying clockdiv 
-tested in spi block
-more generic, simpler
 2016-03-10 11:06:28 -05:00