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v1.0

Mono Color

• 1a4172789e
  Merge 3e8b513822b4d0cdb754865baf8b1050b9e91d1e into 7edfcb5f0506fb854449fbe09598a7ec88bb2067 peteasa 2024-09-27 00:32:30 +00:00
• 7edfcb5f05 Fixing bug from 3 years ago! - If a tree falls in a forest and no one is around to hear it, does it make a sound? main Andreas Olofsson 2024-05-07 23:12:54 -04:00
• 6ea6c039cf
  Merge pull request #116 from volkamir/compilation-fixes Andreas Olofsson 2024-02-14 15:05:57 -05:00
• 6f8df6ebb1 remove unused parameter volkamir 2024-02-09 12:29:22 -08:00
• c1693e9483 add variable definition volkamir 2024-02-09 12:29:06 -08:00
• 3e17b37044
  Create presentation_layout.md ER MOHD ARIF 2024-01-10 12:37:48 +05:30
• c251f75580
  Merge pull request #114 from aolofsson/master Andreas Olofsson 2022-10-17 21:10:13 -04:00
• b8a962e61b Fixing random compile issue with -y include in surelog master aolofsson 2022-10-17 21:06:59 -04:00
• f21be19c28 Simplifying bin2gray converter aolofsson 2022-10-17 21:05:55 -04:00
• 5744252f91 Updating broken fifo (wip) aolofsson 2022-10-05 08:36:41 -04:00
• 69a0dd2d3d Fixing broken empty signal - Snuck in during the wip changes aolofsson 2022-10-04 19:25:59 -04:00
• b741fcb3a9 Adding sc place holder aolofsson 2022-09-29 22:21:04 -04:00
• 2304cf3027
  Update README.md Intubun 2022-08-06 21:44:35 +02:00
• a7e1b2459d
  Update README.md Intubun 2022-08-06 21:43:59 +02:00
• b4d7ea3b74
  Update Readme.md Intubun 2022-08-06 21:41:07 +02:00
• 2ae7a67710 Improving help for lfsr module aolofsson 2022-06-29 08:56:11 -04:00
• 40756aa177 Merge branch 'master' of github.com:aolofsson/oh aolofsson 2022-06-28 23:23:01 -04:00
• 9410821818 Finally converging on a decent lfsr module - Lesson 1: Keep it simple!!! - Lesson 2: Make each program do one thing well. (unix) - Lesson 3: Make module dynamic (parameters and ifdefs are horrible!) - Lesson 4: Synthesis can remove bits set to 0 in design... - Lesson 5: Dynamic binding/programmabiility is better! aolofsson 2022-06-28 23:19:56 -04:00
• 26caf997d3 Finishing minimal icarus "standardized" testbench - Driving all values from the command line - Standardizing around "OH_" to avoid name conflicts - Driving seed as a parameter value aolofsson 2022-06-28 23:18:00 -04:00
• 8ccce92551 Name change... - Calling a random number generator is overstepping.. aolofsson 2022-06-28 21:19:16 -04:00
• 6b0cb3b24d Hard coding values in oh_verify -Match up with stimulus. You can always construct your own using oh_random Andreas.Olofsson 2022-06-27 16:37:17 -04:00
• 7ba6be5a2f Adding siganture checker - Dead simple, just recreate the same lfsr pattern at destination aolofsson 2022-06-27 09:28:29 -04:00
• 5076694f60 New random number generator (wip) aolofsson 2022-06-27 09:28:06 -04:00
• 4b95578d9c Making stimulus module more general - Drive random stimulus, from memory, or bypass aolofsson 2022-06-27 00:27:22 -04:00
• e8bbc6a675 Adding Top level simulation file for icarus - Very thin file with simulation control specific to simulators - A similar file needed for Verilator - The idea is that the testbench can be instantiated in an FPGA/Verilator aolofsson 2022-06-27 00:26:09 -04:00
• ada97a78be Changing testbench hiearchy - A testbench now continaines a dut, standard stimulus module, and in place logic for checking the result. - The result checking in verilog is the hardest part and generally not done well. - For verilator/systemc, we rbing out the checking into software through the interface. - For simple testing like rng based testing or self checking cpu tests, we add the check in verilog at the testbench level on a per dut basis. aolofsson 2022-06-27 00:24:07 -04:00
• a94911808a Changing testbench to be a stub aolofsson 2022-06-27 00:23:48 -04:00
• 3ad1b03fe7 Removing dut feedback loop from simulation control - ...to complicated... - incloding a simple linear test flow for "80%" of foofoo testing - aolofsson 2022-06-27 00:22:02 -04:00
• aeb133be6f Making stimulus memory a portable RAM -Cleaing up some comments and spacing... aolofsson 2022-06-24 22:41:52 -04:00
• ed8a53cdd2 Moving simctrl to testbench - Cleaning up interfaces - Adding more universal parameters to testbench top aolofsson 2022-06-24 22:40:28 -04:00
• 4b3a48a01a Adding testbench to be used in fpga/sim aolofsson 2022-06-24 22:19:33 -04:00
• 822fa009b8 Refactoring simulation control file - Better names (clk1/clk2 was confusing) - Removing supplies (rare special case), handle with ctrl - Remove sting passing parameters for testname, primitive, not useuful aolofsson 2022-06-24 22:17:42 -04:00
• 17cbf190dc Adding stub file for tb_dut wrapper aolofsson 2022-06-24 22:17:21 -04:00
• 354148d176 Fixing cdc linter error aolofsson 2022-06-23 17:50:14 -04:00
• 19f278ddb3 Changing name dv to testbench -Clarity... Andreas.Olofsson 2022-06-22 11:12:51 -04:00
• e631bfe3f1 Fixing naming error -The directory should contain rtl only. -HDL is too broad a term Andreas.Olofsson 2022-06-22 11:04:54 -04:00
• 62e519b52a Directory strcuture change -hdl-->rtl (more common...) aolofsson 2022-06-21 14:59:53 -04:00
• 289024fd89 Flattening directory tree (again) - Creating an arbitrary 'src' directory really doesn't help much... - Goal is to make each folder self contained - Make meta repos and individual repos have the same directory structure aolofsson 2022-06-21 14:48:48 -04:00
• 60fdcbd3e6 Renaming enoc to emesh for consistency aolofsson 2022-06-18 08:51:24 -04:00
• f938b7acac Shorter, better names for rams aolofsson 2022-06-17 23:16:07 -04:00
• 19074173ff Making stimulus a general purpose test vector engine -Should work in an FPGA as well... -Anything that is synthesizable goes into the hdl/rtl directory... aolofsson 2022-06-17 23:04:34 -04:00
• 996d980059 Adding testbench for stimulus -New name, new methodology aolofsson 2022-06-17 23:03:32 -04:00
• f0d0750dae Adding test template for emesh packet format aolofsson 2022-06-17 23:01:40 -04:00
• 1d7dd09b19 Rallying around TARGET for any platform specific RTL aolofsson 2022-06-17 15:10:19 -04:00
• f0372e5afe Adding random pulse generator aolofsson 2022-06-17 15:10:03 -04:00
• d380374049 Adding basic limits to random number generator aolofsson 2022-06-17 15:09:32 -04:00
• 70bbde9ccb Adding basic random HW random number generator -work in progress... aolofsson 2022-06-17 14:40:24 -04:00
• a31e16fb25 Increasing timeout value on simctrl to reasonable default aolofsson 2022-06-17 14:39:23 -04:00
• f6610a0f80 Updating emesh monitor - Removing hard coded name in file (dumb) - Adding support for multiple packet sizes aolofsson 2022-06-17 12:56:46 -04:00
• 46310f842e Changing block name to avoid conflict with "soft" constraints aolofsson 2022-06-12 22:48:14 -04:00
• 5258c5c357 Adding place holder isolation buffers aolofsson 2022-05-29 09:21:10 -04:00
• e89f815b38 Going back to placing all folders in src - Only way to scale, final decision!! aolofsson 2022-05-29 08:45:00 -04:00
• d8b44971b5 Fixing old WIP typo bug aolofsson 2022-05-29 08:43:44 -04:00
• 818ad00d3c Moving mathlib into stdlib -Less libraries is better in this case aolofsson 2022-05-27 22:01:24 -04:00
• 23b26c4a93
  Merge pull request #111 from nmoroze/master Andreas Olofsson 2021-11-26 21:15:20 -05:00
• a7bae72f34 Pass through tech_cfg_width to iobuf Noah Moroze 2021-10-08 18:53:47 +00:00
• 172c1f8732 Make tech_cfg an inout so it can expose tieoffs Noah Moroze 2021-10-07 18:31:34 +00:00
• 24e70f55bd Confusing to have more than one clock for a sync fifo... aolofsson 2021-09-25 22:35:42 -04:00
• 5d4ad5b17b Merge branch 'master' of github.com:aolofsson/oh aolofsson 2021-09-23 09:58:21 -04:00
• eb16df1e3c Fixing syntax errors found by surelog aolofsson 2021-09-23 09:58:08 -04:00
• eeb0b784c4 Add ring port for tech-specific power-ring signals Noah Moroze 2021-08-18 19:31:04 +00:00
• 4942b2509a Fix typo Noah Moroze 2021-08-17 19:32:57 +00:00
• e0abb876da
  Merge pull request #110 from nmoroze/master Andreas Olofsson 2021-08-15 22:49:09 -04:00
• b4f1aa3a60 Add generic cell under oh_pads_corner Noah Moroze 2021-08-13 16:18:37 -04:00
• 3e1d6d8e8d Add parameters to disable POC/cut cells Noah Moroze 2021-08-13 16:18:21 -04:00
• bc9d7f8e55 Insert missing comma Noah Moroze 2021-08-07 17:15:48 -04:00
• d8a28ac153 padring: add pass-through "tech config" for GPIO Noah Moroze 2021-08-05 17:22:05 -04:00
• adb1bf9eae Fix whitespace in oh_padring Noah Moroze 2021-08-05 15:48:45 -04:00
• 88dd3be734 Creating mathlib for arithmetic aolofsson 2021-08-02 18:18:54 -04:00
• 4643670a08 Adding ASICLIB description aolofsson 2021-08-02 18:03:51 -04:00
• 826bf75d2e Removing depracated script in asiclib aolofsson 2021-08-02 18:01:55 -04:00
• 79b1eb5b6c Adding README for asiclib aolofsson 2021-08-02 18:00:13 -04:00
• 1fe01b27d2 File cleanup aolofsson 2021-08-02 17:37:36 -04:00
• 02ee349faa Adding stdlib (in place of common) aolofsson 2021-07-29 11:22:25 -04:00
• de63dfd907 Major reorg! -stdcells moved to asiclib, doesn't make sense to be vectorized -common is a stupid name, renamed as stdlib aolofsson 2021-07-29 11:20:44 -04:00
• 3cb916f4b5 Fixing typo bug in csa32 aolofsson 2021-07-28 18:27:21 -04:00
• aeb391a186 Fixing module name issue aolofsson 2021-07-28 18:25:24 -04:00
• df731e4e13 Adding asiclib scripts directory aolofsson 2021-07-28 08:48:15 -04:00
• 9e41b55f22 Adding default property to all cells -Can be used to select between different cells (like sizes) that have the exact same logical function aolofsson 2021-07-27 22:55:45 -04:00
• 541ed2fbc8 Fixing csa cell to be single bit aolofsson 2021-07-27 22:54:00 -04:00
• 3dbb3755af Adding asiclib -Represent set of cells that need hard coded cells or hard coded gate level designs. aolofsson 2021-07-27 22:24:40 -04:00
• f91d839e11 WIP: Complete refactoring of common lib to support asic cells -Changing DW to N for vector width (uniformity, clarity) -Adding asic cells with SYN statement -Adding TYPE parameter -Moving for loops outside of asic gates -Rename pwr cells to use simpler names aolofsson 2021-07-26 22:34:03 -04:00
• 0a875e193c Removing useless edge detect module aolofsson 2021-07-26 17:28:52 -04:00
• 41e5077f06 Removing depracated iobuf cell (now in padring) aolofsson 2021-07-26 12:02:58 -04:00
• 50d9ebe637 Implemeting new asic cell approach for latches aolofsson 2021-07-26 12:01:50 -04:00
• f298ded0d0 Removing depracated generic fifo aolofsson 2021-07-26 11:50:20 -04:00
• 421fcf6340 Implementign asic cell redirection for clock gates aolofsson 2021-07-26 11:49:10 -04:00
• 916d6c8b3d Implementing asic_cell redirection for csa's aolofsson 2021-07-26 11:46:05 -04:00
• 15c65d2282 Adding clockmux2 and clockmux4 -Cover 99% of all cases clock selectors aolofsson 2021-07-26 11:44:17 -04:00
• 10421758bc Adding asic cell to buffer -Note that asic cells should not be vectorized -Simplifies implementation (per target) aolofsson 2021-07-26 11:33:12 -04:00
• edaa41dac7 Adding asic_add block to abs circuit aolofsson 2021-07-26 11:32:43 -04:00
• e82fdb65a1 Adding asic_add to counter aolofsson 2021-07-26 11:32:19 -04:00
• 9e8263b17d WIP: Making delay programmable based on selector -More generatlized than a statically compiled parameter -Synthesis engine should optimize away redundant logic aolofsson 2021-07-26 11:30:29 -04:00
• f2f1e10ebe Removing 8b/10b -Not curated aolofsson 2021-07-26 08:47:08 -04:00
• 2ad5e665d2 Adding asic instantiation to arithmetic blocks aolofsson 2021-07-26 08:43:05 -04:00
• 2e42e174d8 Rewrite of oh_tristate -The previous implementation was really an io pad buffer, which belongs in the padring library -New implementation is a true tristate buffer that can be mapped to an stdcell aolofsson 2021-07-26 08:41:38 -04:00
• 2424d929f7 Adding behavioral vs asic distinction to shifter/adder aolofsson 2021-07-26 08:21:09 -04:00
• 50c1845f30 Adding synthesizable multipler aolofsson 2021-07-26 08:19:50 -04:00
• 2dd46abdd1 Fixing compiler warnings aolofsson 2021-07-25 15:16:52 -04:00
• eb162a3bf3 Changing ifdef to generate statement aolofsson 2021-07-25 15:04:44 -04:00