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v1.0

Mono Color

• 141505c638 WIP: Significant reorg -Fixing compile errors from previous WIP -Flattening code structure further for ease of navigation -Changing to "SYN" for synthesizable code -Name changes for clarity (PS-->SYNCPIPE) - aolofsson 2021-07-25 14:46:55 -04:00
• 6df5f8bdb4 Merge branch 'master' of github.com:aolofsson/oh aolofsson 2021-07-24 23:30:05 -04:00
• 59e8d046da Compilation cleanup aolofsson 2021-07-24 23:29:50 -04:00
• b52c45d119
  Merge pull request #109 from nmoroze/master Andreas Olofsson 2021-07-24 22:11:39 -04:00
• b36d31290a Fix width of padring 'dout' ports Noah Moroze 2021-07-06 17:51:24 -04:00
• a95510103e
  Merge 53e56bbd2518a31082723814da915d877460f484 into 4556136e7bc44617e37ce9aa5fcead2e1ad26383 Ola Jeppsson 2021-06-27 23:13:45 -07:00
• 4556136e7b Removing depracated file -Power merged with domain aolofsson 2021-06-16 17:00:31 -04:00
• 7a136c39d8 Adding basic padring generator aolofsson 2021-06-16 10:49:18 -04:00
• bbc0e979d2 Whitespace cleanup to domains file aolofsson 2021-06-16 09:33:13 -04:00
• d6e18791b5 Adding place holder core power pad cell aolofsson 2021-06-15 11:57:48 -04:00
• 403976b8c9 Adding corner pad place holder aolofsson 2021-06-15 11:48:39 -04:00
• 3601fa409b Adding place-holder cell for padring aolofsson 2021-06-15 11:45:10 -04:00
• acc72c5762 Removing netlist directory -All abstracted information contained in hdl aolofsson 2021-05-26 14:57:25 -04:00
• d0dab83075 Merging rtl and switch models in one verilog file aolofsson 2021-05-25 19:27:00 -04:00
• 2eb3e4518b Prototype for driving cell level parameters aolofsson 2021-05-25 16:10:50 -04:00
• 2e8551d468 Adding nor primitive circuit aolofsson 2021-05-25 13:57:16 -04:00
• b2624e803e Adding switch level modeling of nand gate aolofsson 2021-05-25 13:48:00 -04:00
• 3fc3983494 Fixing concatentation errors aolofsson 2021-05-24 20:56:48 -04:00
• 9631c50bae Adding scan cells to standard cell libs aolofsson 2021-05-24 20:52:04 -04:00
• f4184b048a Adding xor standard cell family aolofsson 2021-05-24 20:30:20 -04:00
• 5e151efa51 Adding batch of oa/ao cells aolofsson 2021-05-24 20:26:05 -04:00
• a08ef0d84c Fixing nset typo aolofsson 2021-05-24 20:25:55 -04:00
• 0489dd2d8c First batch of standard cells aolofsson 2021-05-24 19:05:20 -04:00
• a0625a7d0f Adding WIP/broken warning aolofsson 2021-04-26 10:26:24 -04:00
• 3c6c41ff83 Removing depracated eda directory aolofsson 2021-04-26 09:39:36 -04:00
• 3977791929
  Merge pull request #108 from aolofsson/pr_aolofsson Andreas Olofsson 2021-04-26 08:58:44 -04:00
• 65a13b5067 Merge branch 'master' of github.com:aolofsson/private-oh into pr_aolofsson pr_aolofsson aolofsson 2021-04-26 08:56:16 -04:00
• ff4ddf28d8 Dummy commit aolofsson 2021-04-26 08:44:21 -04:00
• 3911ad8c6e Using autoinst feature for fifo_sync aolofsson 2021-04-18 22:30:13 -04:00
• 2ca5343322 Updating latch syntax to fix Foss parsing issues aolofsson 2021-04-18 22:29:27 -04:00
• 413d1dec32 Addding full interface to memory -If you are going to instantiate a hard instance, you might as well do it right. For tools that generate these interfaces, who cares -For debugging, nothing is worse than traversing an endless set of wrappers. -Bigger interfaces are better than more levels aolofsson 2021-03-02 16:49:49 -05:00
• 9b63e23bda Adding always_latch to avoid verilator warnings aolofsson 2021-03-02 16:49:20 -05:00
• 1925c188c8 Fixing compilation error Andreas.Olofsson 2021-03-02 15:36:33 -05:00
• 3e49fa499f Making almost full programmable in oh_fifo_sync Andreas.Olofsson 2020-12-07 16:58:47 -05:00
• 401d1c2e93 Adding a generic single/dual/soft/hard memory macro Andreas.Olofsson 2020-12-04 15:58:53 -05:00
• 490ce22244 Flattening memory hierarchy!!! -Now completely compatible with FPGA and ASIC flows with a single source Andreas.Olofsson 2020-12-04 15:58:07 -05:00
• 7ff50650f7 Changing name back to "oh_mem_dp" -Now moving to make the names the change, note that since there are many different designs within one SoC/compilation, you will need to have a large if-else somewhere on the design or an automated compiler for each project. -I saw you have one file asic_mem that contains all the macros in the design with if-else statements inside -Is there a situation where you would want to decide top what implementtaion you wnt. -For example, you might want flip-flops sometimes, and other times perhaps a different aspect ratio? -How to drive the floor-planning, by running experiments, not hard coding!!! -A designer might want to choose (tall, wide, square, for hard macros) -Also need to specify hard/soft on a per macro basis Andreas.Olofsson 2020-12-04 12:39:45 -05:00
• b62c11cf67 name change from memory_sp to sram_sp Andreas.Olofsson 2020-11-02 15:01:50 -05:00
• 022563c414 Name change for enoc packet to avoid signal confusion Andreas.Olofsson 2020-11-02 14:54:29 -05:00
• 7b5e6a2380 MILESTONE: New enoc pack/unpack compiles! Andreas.Olofsson 2020-10-15 11:45:17 -04:00
• 38cb339eda MILESTONE: New version of enoc command structure Andreas.Olofsson 2020-10-15 10:58:39 -04:00
• ed0f43a031 MILESTONE: Solidified enoc command decode -making IO memory mapped, should be invisible to user! -don't push micro optimiation onto programmer! -don't confuse user with implementation concerns, renaming input to input, output to output for packing! Andreas.Olofsson 2020-10-15 10:19:34 -04:00
• 046480bfb3 Adding enoc common opcode decode file Andreas.Olofsson 2020-10-15 10:12:40 -04:00
• 798634a9c5 Renaming emesh as enoc (better description) Andreas.Olofsson 2020-10-15 09:38:12 -04:00
• f6b9f6cad7 Upating packet2emesh with new format. -Moving sa0/sa1 in order to simplify -With the new clean format there is no need for the split Andreas.Olofsson 2020-10-09 22:10:57 -04:00
• 7c05557e6f MILESTONE: Yet another major revision of emesh protocol -Remove formats and rally around 16bit CMD,simplicty over optimization! -Need to think of being scalable enough for 64bit memory and cache coherent systems!!!! The cost of this forward looking compatibility is only 8 bits, when compared to the 128 bits minimum of address/data pair, this is acceptable Andreas.Olofsson 2020-10-09 21:54:33 -04:00
• 558776a3b3 MILESTON: New packet format created for emesh Andreas.Olofsson 2020-10-09 13:18:03 -04:00
• 8268480640 MILESTONE: Implemented new packet command -AW16 to AW128 Andreas.Olofsson 2020-10-07 10:36:37 -04:00
• 0b91be7a75 New extended packet formats for emesh Andreas.Olofsson 2020-10-07 09:28:57 -04:00
• e123650d06 Major change of "wait" to "ready" -This will cause a lot of nasty bugs, but it's the right thing to do to be more consistent with standard buses going forward. -Change is made from access/wait tp valid/ready Andreas.Olofsson 2020-09-26 12:33:13 -04:00
• a3f08449e2 Simchecker printout fix Andreas.Olofsson 2020-09-26 12:32:38 -04:00
• 58aabca0aa IOBUF name changes -Separating pullup and pulldown signals -Changing direction of in/out names to avoid confusion -direction is now with reference to the core Andreas.Olofsson 2020-09-23 16:49:34 -04:00
• c215b48a55 Redesining oh_iddr -adding separate clock enables -adding internal clock enable for neg edg sample -combining q1/q2 legacy interfae into a single output Andreas.Olofsson 2020-09-23 16:48:10 -04:00
• fda0f35dd9 Name change to packets -Using valid signal instead of access, more standardized Andreas.Olofsson 2020-09-23 16:47:13 -04:00
• f817bb57ec Removing redundant code in async fifo instance Andreas.Olofsson 2020-09-23 16:46:46 -04:00
• acd469e933 Removing extra pipeline dela in ODDR -Both din1 and din2 needs to be stable low by driver -If the inputs are driven by a reg anyway like in the case of a FIFO output or memory, then we just saved a cycle of redundant latency Andreas.Olofsson 2020-09-22 10:57:00 -04:00
• 6be20de08b Day zer big???!!! -Can't believe this was missed!!!!! -Clearly for a dual data rate circuit, a stable low signal should be selected with low clock, that's the definition! Andreas.Olofsson 2020-09-22 10:31:38 -04:00
• 30419a5239 Adding generic IO buffer Andreas.Olofsson 2020-09-21 13:54:06 -04:00
• 98b7494678 Future proof emesh format with another byte of controls -At 144 bits, it's less than 5% in signals and virtually no power penalty -The goal is to be completely axi feature compliant Andreas.Olofsson 2020-09-21 09:20:22 -04:00
• 89f995c20c Fixed nasty testbench problem that snuck in -The pass fail indicator is always tricky to get right -In this case diff/done went high on the same cycle so everything was passing.. -Added check for same cyle completion/fail -Also, changed the top level anme to "testbench", seems more popular Andreas.Olofsson 2020-08-19 19:34:03 -04:00
• 028dcd886d Bug fix, adding missig reset signal Andreas.Olofsson 2020-08-17 23:16:06 -04:00
• ec26479567 Adding missing ports to dual port memory -Seems excessive? Andreas.Olofsson 2020-08-17 23:15:00 -04:00
• bc76414aa5 Fixing crucial reset bug in dsync Andreas.Olofsson 2020-08-17 23:14:21 -04:00
• 6d1735d3b9 Fixing a bunch of synthesis issues -Better to fix to avoid issues across different synthesis platform (even if standard would allow if for verilog2005) Andreas.Olofsson 2020-08-17 16:11:42 -04:00
• 6ae99dbba4 Fixing priority problem withy pass/done -When diff gets stuck high, test would timeout Andreas.Olofsson 2020-08-17 16:10:03 -04:00
• 58ee16092e Changing simchecker to hex. -Not practical for broad use with binary Andreas.Olofsson 2020-08-17 16:09:32 -04:00
• 76e6cd3c15 Fixing concatenation bug -Don't use concatenation for generators! -Will failt for DW=1 Andreas.Olofsson 2020-08-14 10:38:03 -04:00
• 5c0df270c5 Belated fix of register file -Simulated correctly, but did not synthesize in DC Andreas.Olofsson 2020-08-08 22:23:45 -04:00
• 0d61520268 Fixed issue with DC verilog parser -Apparentely "|=" is not allowed?? Andreas.Olofsson 2020-08-08 22:22:52 -04:00
• d7769070fc Adding diff and sticky flag to ease debugging -One flag for end of test pass fail -Seond flag for gtkwave to see where all the fails happen Andreas.Olofsson 2020-07-27 19:56:57 -04:00
• 7abc91751a Fixing basic register file bug -Working in simulation but was not synthesizable by DC Andreas.Olofsson 2020-07-27 19:56:11 -04:00
• 9147a49103 Fixing basic carry bug in the csa4:2 (carry was wrong) Andreas.Olofsson 2020-07-20 22:51:58 -04:00
• ae6cdc912e Mapping cs42 to csa32 -Better synthesis results Andreas.Olofsson 2020-07-20 14:50:09 -04:00
• 9ac530e526 Adding indication that test started for regression clarity Andreas.Olofsson 2020-07-19 10:12:07 -04:00
• 84e8449cb5 Moving sampling to negedge for clarity Andreas.Olofsson 2020-07-14 13:50:24 -04:00
• 126f859908 Adding clock enable for register -Removing the ASIC CFG as well...have to rethink that concept, not really working Andreas.Olofsson 2020-07-14 13:48:42 -04:00
• d7639390f4 Typo fix Andreas.Olofsson 2020-04-23 22:44:47 -04:00
• 58eedb914d Cleanup Andreas.Olofsson 2020-04-22 23:17:25 -04:00
• 7c0e1bc01f Adding fail criteria to common simulation control infrastucture -Preparing for CI and unit tests for all modules Andreas.Olofsson 2020-04-22 23:16:43 -04:00
• 2c106bed5e Moving checker to positive edge -This should be synthesizable into FPGAs! Andreas.Olofsson 2020-04-22 23:15:41 -04:00
• a7870ac9de Cleaned up counter -Not functional Andreas.Olofsson 2020-04-22 23:15:12 -04:00
• d8d2d0c20e Changing dv_checker to oh_simchecker -library consistency Andreas.Olofsson 2020-04-22 22:40:43 -04:00
• cf47e56436 Changing dv_* to oh_* to be consistent Andreas.Olofsson 2020-04-22 21:52:37 -04:00
• d9897a1bec Multi-type multiplier working -only reference model implemented -Next, implement complete algorithm and output partial products Andreas.Olofsson 2020-04-09 21:42:28 -04:00
• d6b6e1bd76 Adding basic multiplier stub Andreas.Olofsson 2020-04-09 14:58:29 -04:00
• 97bc8d08af Name change one last time... Andreas.Olofsson 2020-04-07 10:25:54 -04:00
• 8b39f7e444 Fixing register file -Changing DW to RW (RW not always equal to DW..) -Blocking rd_data on valid -Fixing elemetary bugs based on indices -Simplifying index code -Add configurable pipeline stage? Andreas.Olofsson 2020-04-07 10:23:35 -04:00
• 68829c93d0 Adding dumpvar to interface Andreas.Olofsson 2020-04-02 22:14:07 -04:00
• 32b103d290 Adding parametrized register file Andreas.Olofsson 2020-04-02 22:13:07 -04:00
• 18bb820f56 Merge branch 'master' of github.com:aolofsson/private-oh Andreas.Olofsson 2020-03-28 15:40:11 -04:00
• c271360709 Changing order of RAM array Andreas.Olofsson 2020-03-28 15:38:29 -04:00
• 65aa1b061c Rewritten trace script for spike -ovpsim is a dead end, good bye Andreas.Olofsson 2020-03-28 15:37:10 -04:00
• 281a19d7bf Adding debug features to fifo_sync -Ability to dump array -Error on attempt to write to fifo while full Andreas.Olofsson 2020-03-26 12:24:45 -04:00
• 5269354461 Adding ability to dump array for iverilog -Important for FIFO debugging Andreas.Olofsson 2020-03-26 12:24:01 -04:00
• 064ec792d3 Adding testname to simplfy grepping of regression suite results Andreas.Olofsson 2020-03-26 12:22:56 -04:00
• cbb8f79fd2 Inverting polarity for compiler Andreas.Olofsson 2020-03-26 12:20:00 -04:00
• bf277f3d2f Adding offset removal to script -Allows us to remove the pesky 0x80000000 from the RV infrastucture -They refuse to fix the boot sequence in spike for bare metal -This is the workaround Andreas.Olofsson 2020-03-26 12:18:59 -04:00
• 7b33ff0405 Fixing yet another fifo bug... Andreas.Olofsson 2020-03-20 20:39:15 -04:00
• 3c8be0c083 Fixing brain-dead bug! -I guess nobody has been using this fifo, because it was hoplessly broken. Fucking sad. Andreas.Olofsson 2020-03-13 12:24:35 -04:00
• bee941aa61 Adding reset wakup event to standby module -Create an event at rising edge of reset -Turn on the clock for long enough to allow for reset signal to get turned on -Note the race here! This is why the rest and standby needs to be combined into one block. Andreas.Olofsson 2020-03-13 11:05:49 -04:00