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  • 049a031e47 common/hdl: Fix syntax error when CFG_ASIC is undefined Ola Jeppsson 2017-02-03 02:26:37 +01:00
  • 6a50842b46 zcu102: Update block design Ola Jeppsson 2017-02-03 00:48:17 +01:00
  • 094f417f66 zcu102: Add package pins for FMC0 connector Ola Jeppsson 2017-02-03 00:47:18 +01:00
  • bac760678c Add zcu102 design Ola Jeppsson 2017-02-01 11:07:31 +01:00
  • 440005fbc0 common/fpga/create_ip.tcl: Add Ultrascale+ to supported families Ola Jeppsson 2017-01-31 18:49:12 +01:00
  • 12e7b5ad14 ip: fifo_async_104x32: Switch to ultrascale device Ola Jeppsson 2017-01-31 18:42:47 +01:00
  • 83a37d2469 ip: fifo_async_104x32: Update to Vivado 2016.4 Ola Jeppsson 2017-01-31 13:42:59 +01:00
  • 1916ab8777 docs: Fix GPIO description Raphael Nestler 2016-06-29 15:41:03 +02:00
  • e7abddbcb5 Adding planning document for boards -Not CAD accurate, only for visual planning Andreas Olofsson 2016-12-21 12:05:37 -05:00
  • b350deb827 Adding directory of standards -Summary Andreas Olofsson 2016-11-15 06:51:39 -05:00
  • d1f9bdffbb Adding place holder definition for open source Andreas Olofsson 2016-10-24 11:24:08 -04:00
  • 63f77ef832 Format change for board record - explicit link - adding docs Andreas Olofsson 2016-10-24 11:17:45 -04:00
  • 8e195c4d17 Cleanup Andreas Olofsson 2016-10-24 10:57:24 -04:00
  • 6546787c77 Adding Rascal board Andreas Olofsson 2016-10-24 10:52:24 -04:00
  • e7745a3bec Link cleanup Andreas Olofsson 2016-10-24 10:33:30 -04:00
  • 3ac57dabba Adding open source board resource Andreas Olofsson 2016-10-24 10:27:58 -04:00
  • 383cda2550 Adding preliminary r5 opcodes Andreas Olofsson 2016-09-26 15:16:00 -04:00
  • 5a583c598c Adding buffer - Sometimes you need to instatiate buffers manually in RTL to get around some absolutely braindead behaviour in eda tools. Not often, but sometimes... Andreas Olofsson 2016-09-03 14:59:30 -04:00
  • 70533b57b0 Refactoring asic code - remove redundant hierarchy - using shorter/better names to make sdc constraints less ugly Andreas Olofsson 2016-09-03 14:40:51 -04:00
  • 94469ed5f4 Resetting shift register - Less red to look at... Andreas Olofsson 2016-09-03 14:40:21 -04:00
  • a306aa5178 Removing one level on redirection on clockor - It was getting annoying.... Andreas Olofsson 2016-09-02 00:39:32 -04:00
  • 128c4015b3 Adding reset to wakeup pipeline - Suspect behaviour when clock is absent.. Andreas Olofsson 2016-09-01 19:32:48 -04:00
  • 0f8beea513 Fixing reset bug for MIO emode - Shows up when there is no free running clock. Don't assume there is a clock at startup! Andreas Olofsson 2016-08-28 19:14:45 -04:00
  • 3e18d921d6 Adding DV hook into SPI block - Inputting large amount of data through SPI in DV is soooo painfully slow. Added hook to speed up development. 100x speedup in verification time-->100x speed up in design team. Andreas Olofsson 2016-08-26 23:50:05 -04:00
  • dc22df0d5c Fixing MIO synthesis errors/warnings Andreas Olofsson 2016-08-26 00:41:42 -04:00
  • a13b665027 SPI synthesis cleanup Andreas Olofsson 2016-08-26 00:40:09 -04:00
  • ac735cba6a Fixing MIO emesh transaction bug - data should go straight into fifo for first cycle - after that, the data is taken from a temporary buffer Andreas Olofsson 2016-08-25 21:01:44 -04:00
  • 073d003e40 Fixing MIO transmit DDR mode -iowidth refers to the size of a single ended bus -DDR is implicitly half that size Andreas Olofsson 2016-08-25 21:01:01 -04:00
  • ebeeb1dd8b Fixing bug in MIO receiver -nibble wide io now supported in RX Andreas Olofsson 2016-08-25 21:00:34 -04:00
  • c566f46a60 Adding missing parameter in MIO Andreas Olofsson 2016-08-25 17:53:02 -04:00
  • 988d4dbd94 Fixing MIO mode switch bug - Need to look over this circuit again, feels nasty. There is a ever rotating state here, that should probably be reset when there is no transaction, but how? Andreas Olofsson 2016-08-25 17:29:55 -04:00
  • a65bfafbb6 Fixing MIO DDR mode Works! Andreas Olofsson 2016-08-25 17:29:29 -04:00
  • ae8264afc1 MIO interface changes cleanup Andreas Olofsson 2016-08-25 15:43:55 -04:00
  • c9046cd645 Implementing amode/emode receiver -emode debugged, working!! Andreas Olofsson 2016-08-25 15:43:27 -04:00
  • ae24a4754c Changing to datamode in rx - More standard Andreas Olofsson 2016-08-25 15:42:48 -04:00
  • 97ef662e38 Fixing various simple MIO receiver IO bugs - Really a nice reverse of TX logic... - Support for partially full transfers when frame goes low Andreas Olofsson 2016-08-25 14:15:40 -04:00
  • 401b0a64f9 Connecting missing clock Andreas Olofsson 2016-08-25 14:15:25 -04:00
  • 5ee15b4802 Fixing default config for new register file Andreas Olofsson 2016-08-25 12:40:29 -04:00
  • 75267a539e Fixing bugs in transmit logic - Serializer wait was missing - Need to reload on last cycle before emptying to avoid stall, need "next" Andreas Olofsson 2016-08-25 12:39:16 -04:00
  • e36519138a Adding extra cycle to make number of bytes even - Needed for ddr operation - Enables IOW=16 for sdr mode Andreas Olofsson 2016-08-25 12:38:34 -04:00
  • ac90486cb1 New MIO interface - Work in progress, compiles but not yet debugged Andreas Olofsson 2016-08-25 11:57:28 -04:00
  • f560a5fc20 Adding iowidth as dynamic parameter for MIO Andreas Olofsson 2016-08-25 11:56:42 -04:00
  • f6cb0bb7bf Redesigning MIO rx - Standardize on 64bit FIFO interface - Stuff bytes into shifter register before transferring to fifo - Use valid bits per byte to keep track of valid data through pipe - Work in progress... Andreas Olofsson 2016-08-25 11:55:06 -04:00
  • 1b24fabe15 Adding missing wait signal to rx Andreas Olofsson 2016-08-25 11:54:54 -04:00
  • 9919a34c44 Adding iowidth as parameter to MIO Andreas Olofsson 2016-08-25 11:54:36 -04:00
  • 9e7e771898 Fixing non-blocking bug in dv Andreas Olofsson 2016-08-25 11:45:20 -04:00
  • bfb03e31b3 Fefactoring to clarify register usage Andreas Olofsson 2016-08-25 11:44:30 -04:00
  • 4354a46dce Adding new fifos for MIO -In preparation for redesign Andreas Olofsson 2016-08-25 11:43:48 -04:00
  • 290da8ce48 Adding missing reset synchronization Andreas Olofsson 2016-08-25 11:42:31 -04:00
  • e51d628ed4 SPI code cleanup Andreas Olofsson 2016-08-25 09:02:14 -04:00
  • 4c6cdcaf74 Fixing nasty glitch bug on clock -Created phantom event simulator -Lucky to catch it quickly -Don't know wtf i was thinking with that circuit... Andreas Olofsson 2016-08-24 01:14:05 -04:00
  • f7ce7b800c Fixing spi controller - Manually merging work from @olajep in PR #85 (too far out of sync) - Fixing issue with lsbfirst logic - Adding logic for manual control of slave select - Fixing status register for polling reads - Still a timing/glitch issue on mosi, fix it later... Andreas Olofsson 2016-08-24 00:20:51 -04:00
  • f4a74b462f Adding manual control of slave select pin Andreas Olofsson 2016-08-24 00:19:46 -04:00
  • b9a9853753 Linking test file, copying around sources is really bad... Andreas Olofsson 2016-08-24 00:18:25 -04:00
  • e5b35f611e Merge pull request #96 from peteasa/AugFixes Andreas Olofsson 2016-08-23 18:15:05 -04:00
  • fa7d6f7c2e Changing latching responsibility in clock mux - Ugly to put latch inside the clock mux, there are situations when there is no clock. Need to have complete control over reset and sampling clock, so better to put latch outside of the clock mux..more legoish.. Andreas Olofsson 2016-08-23 17:27:17 -04:00
  • 80c4221b14 Merge branch 'master' of github.com:parallella/oh Andreas Olofsson 2016-08-23 17:15:03 -04:00
  • 7e80a82547 oh_add: Fix typo in the function description Matt 2016-08-21 17:02:46 +02:00
  • a8ef3748bd AXI: emaxi: added nreset to instantiation of oh_dsync Peter Saunderson 2016-08-17 15:57:25 +01:00
  • e781f39e5e TARGET changed back to XILINX from GENERIC Peter Saunderson 2016-08-17 15:30:38 +01:00
  • 553ee31400 Synthesis: parameter = `CFG_ASIC not accepted in module declaration Peter Saunderson 2016-08-17 15:06:01 +01:00
  • 55118cee9d Apply CFG_ASIC at the top level Peter Saunderson 2016-08-17 14:22:04 +01:00
  • b9b42bd93e fixed sort order RainerWasserfuhr 2016-08-05 21:49:20 +02:00
  • aac3d5b3a2 Synthesis cleanup Andreas Olofsson 2016-07-24 05:11:47 -04:00
  • 67409dba7a Simplifying names to make it easier to specify generated clocks Andreas Olofsson 2016-07-09 20:32:57 -04:00
  • 2c272e7afa Synthesis cleanup - adding missing reset on pulse/edge detectors - disconnecting unused signals in spi clockdivider - changin output to input on spi_slave_io for read data Andreas Olofsson 2016-07-09 20:31:00 -04:00
  • b8ef013874 Cleanup (missed a port in last fix removing supply ports) Andreas Olofsson 2016-07-09 17:04:24 -04:00
  • b1871f1867 Fixing clock divider - asic needs a fixed cell for generated clock constraints - fixing glitching on selectors, sampling with latch before mux (stable high) Andreas Olofsson 2016-07-09 17:03:07 -04:00
  • 6b050220d8 Removing dangling supply nets Andreas Olofsson 2016-07-08 19:56:23 -04:00
  • e0fbe6e1ac Merge 4b9e555472eeac45e59b94990439b8a4b86423ac into f2086c5e6927112cf472b9af65171d3e087b584d Ola Jeppsson 2016-06-26 23:20:25 +00:00
  • c0dde5652b Merge branch 'master' of github.com:parallella/oh Andreas Olofsson 2016-06-26 10:02:24 -04:00
  • f2086c5e69 Asic lib cleanup -moving back to generic asic cells after all.. -fixing parameter issue in memory module -named block issue (genblk warning) Andreas Olofsson 2016-06-25 00:04:25 -04:00
  • 8b95b37c85 The asiclib is not generic - Should be "gate level" design Andreas Olofsson 2016-06-24 22:37:06 -04:00
  • b4337d9aba Adding flip-flopr asic wrappers Andreas Olofsson 2016-06-24 22:36:27 -04:00
  • 71f3271074 Adding sampling clock for latch - Should be independent of the clocks being selected Andreas Olofsson 2016-06-24 22:11:36 -04:00
  • 56e7037254 Adding clock "or" circuit Andreas Olofsson 2016-06-24 22:11:23 -04:00
  • 74b26a285f Removing supplies from isolation cells - Was unnatural Andreas Olofsson 2016-06-24 21:30:34 -04:00
  • 186b337a45 Cleanup of common files using cells that use asic cells - ASIC/PROJ changes Andreas Olofsson 2016-06-24 21:26:14 -04:00
  • bc515f9308 Adding isolation block for tie high - Needed for active low reset signal Andreas Olofsson 2016-06-24 21:25:41 -04:00
  • a45155a4e6 ASIC config parameter simplication - Hiding project name, is a true "global". It defines the flavor of the project and will never be overridden at instantiation...so fine - Adding CFG_ASIC as a default in parameter statement...because generally you need the ability to override but carrying it all the way through the hierarchy is just annoying... Andreas Olofsson 2016-06-24 20:34:49 -04:00
  • 2623d2239e Adding asiclib cell for lat0 Andreas Olofsson 2016-06-24 20:34:32 -04:00
  • 893db9508a Merge branch 'master' of github.com:parallella/oh Andreas Olofsson 2016-06-20 21:21:07 -04:00
  • b866045861 Making DELAY a cell parameter Andreas Olofsson 2016-06-19 17:36:00 -04:00
  • ef2e3248a3 Adding parameter guideline - You will be chasing this bug, if you ever add a parameter... Andreas Olofsson 2016-06-19 17:35:18 -04:00
  • aa1e511a30 Moving xilibs/hdl to xilibs/dv - HDL should always be synthesizable... Andreas Olofsson 2016-06-19 17:18:44 -04:00
  • 40da0fe14a Synthesis cleanup Andreas Olofsson 2016-06-19 17:12:24 -04:00
  • 73c1c496cb Cleaning up SPI chip synthesis errors/warnings - Better to clean up than to have every designer setting an "ignore warning" in tool. - Don't fight the tools... Andreas Olofsson 2016-06-19 17:11:33 -04:00
  • 3151b17b93 Cleaning up chip synthesis errors/warnings Andreas Olofsson 2016-06-19 17:10:51 -04:00
  • 61980721f6 Changing synchronizers to scalars - The act of putting in a synchronizer should be scalar! - Putting in vectors should be hard and explicit (thus we make them scalars) - This is in contrast to most other cells which are vectorized by default - "which one is not like the others applies to this cell" - Also cleaning up some chip synthesis warnings/errors Andreas Olofsson 2016-06-19 17:08:46 -04:00
  • 381ba09617 Making CFG_ASIC a primary variable -Need to separate between open FPGA design and closed ASIC design. -NDAs means it's imposssible for us to disclose even the interfaces of the cells inside without taking the risk of violating the terms of the NDA. -For this reason, we come up with generic and clean asic library interfaces that need to be implemented in each library/technology Andreas Olofsson 2016-06-19 17:05:50 -04:00
  • 5706b65d87 Merge 838c14929bd69dbb6eceda5e2bf3624377bfebb9 into 1045e46b0e4fc36be4b8e2d861cec54067d5279c Ola Jeppsson 2016-06-07 20:56:51 +00:00
  • 070676b31d Merge eb4a488b15c17e64cd4390723c19e5fd178542af into 1045e46b0e4fc36be4b8e2d861cec54067d5279c Ola Jeppsson 2016-06-07 20:55:36 +00:00
  • 1045e46b0e Merge pull request #92 from olajep/mio-driver Andreas Olofsson 2016-06-06 05:12:39 -04:00
  • 0ccee8f82f mio: hello-mio: More extensive testing Ola Jeppsson 2016-06-03 19:14:49 +00:00
  • eb4a488b15 mio: axi_mio: Drop io prefix for io signals Ola Jeppsson 2016-06-03 12:23:32 +02:00
  • 95f39a9817 mio: axi_mio: Connect rest of AXI master channels Ola Jeppsson 2016-06-03 11:22:05 +02:00
  • d4940d9798 mio: axi_mio: Simplified but working version Ola Jeppsson 2016-06-02 19:31:47 +02:00
  • ca3c9fdeaf mio: dv: Add test for register read Ola Jeppsson 2016-06-02 11:19:18 +02:00
  • 424fa82a96 mio: mio_regs: Reset all bits of config register Ola Jeppsson 2016-06-02 11:10:56 +02:00
  • 08f467589c mio: dv: dut_mio: Support register reads Ola Jeppsson 2016-06-02 10:41:09 +02:00