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  • 78422215e7 GPIO: Add AXI GPIO module Ola Jeppsson 2016-04-28 00:48:41 +02:00
  • de8d7b7132 GPIO: Fix hardcoded address width Ola Jeppsson 2016-04-28 00:35:38 +02:00
  • 9d5085a4e4 Merge fb42054141adff9d88dd2de823b13bbe79e02a6b into 6b72eab0fe3bf75eb249cc022a4a3e4ea0d4fa48 Ola Jeppsson 2016-04-26 15:05:23 +00:00
  • fb42054141 esaxi: Explicitly reset timeout counter on reset Ola Jeppsson 2016-04-26 16:12:14 +02:00
  • b7b8a9955b GPIO: kernel: Fix bug in oh_gpio_set_value Ola Jeppsson 2016-04-22 16:19:16 +02:00
  • e5413eed8e [RFC] GPIO: Change behavior of IMASK Ola Jeppsson 2016-04-20 18:02:59 +02:00
  • 22f36ce93d Merge pull request #69 from olajep/linux-gpio-driver Andreas Olofsson 2016-04-22 08:24:31 -04:00
  • 2ae9c2420a GPIO: Add linux kernel driver Ola Jeppsson 2016-04-22 13:17:00 +02:00
  • 08cc5fef8f Merge e9185a664e3351feecb402dfc30151cf9eed78e8 into 23cdb8d8d4ed682106903be60e02f5f988c993f1 Ola Jeppsson 2016-04-22 11:21:34 +00:00
  • e9185a664e GPIO: Add linux kernel driver Ola Jeppsson 2016-04-22 13:17:00 +02:00
  • 0ecf9087a0 GPIO: Move gpio library to separate directory Ola Jeppsson 2016-04-22 12:43:17 +02:00
  • 23cdb8d8d4 Adding clock mux with integrated clock gater Andreas Olofsson 2016-04-19 22:55:29 -04:00
  • 5e8c53f619 Tweaking isolate block - removing power signals for now - adding asic parameter Andreas Olofsson 2016-04-19 22:54:30 -04:00
  • 8e23abbc98 Standby bug fix (floating clk) Andreas Olofsson 2016-04-19 22:54:00 -04:00
  • 05f73e200d Improving standby circuit - removing reset (bad logic) - refactor for simplicity/clarity - interface changes Andreas Olofsson 2016-04-19 16:23:50 -04:00
  • 2d3fb8d94c Making clock gater asic friendly - removing reset, shouldn't be in logic - instantiating asic integrated clock gating cell - removing vectorization, shouldn't be here Andreas Olofsson 2016-04-19 16:19:26 -04:00
  • 6742976401 Fixing more synthesis warnings Andreas Olofsson 2016-04-17 10:37:08 -04:00
  • 4e513cfcce Fixing synthesis compilation warnings - Could supress warning printout, but you can't control people's synthesis scripts. Better to fix once than N times... Andreas Olofsson 2016-04-17 09:49:07 -04:00
  • 96e13629aa Fixing standby block - Was missed because block was never instantiated... - Iverilog not very particular..not a great linter Andreas Olofsson 2016-04-17 09:47:55 -04:00
  • 8b24139be1 Adding ASIC parameter to special library functions - Needed to map to specific proprietary libraries - Need to hide actual cells behind abstraction due to NDA Andreas Olofsson 2016-04-15 23:25:49 -04:00
  • 3314051934 Adding delay cell Andreas Olofsson 2016-04-15 23:25:16 -04:00
  • a330f73838 Fixing readme Andreas Olofsson 2016-04-15 22:38:06 -04:00
  • 397b10946f Shortening flow names - + reorg Andreas Olofsson 2016-04-15 22:32:27 -04:00
  • 09e40875bb Adding wrappers for pnr Andreas Olofsson 2016-04-15 18:01:09 -04:00
  • 8bfccdfd73 Simplifying synthesis flow - Too many steps, some of them were "one line long" Andreas Olofsson 2016-04-15 17:37:32 -04:00
  • 53dea826bc Merge branch 'master' of github.com:parallella/oh Andreas Olofsson 2016-04-14 15:55:16 -04:00
  • d237c17eba Instantiating generic ram module in dp memory Andreas Olofsson 2016-04-14 15:54:50 -04:00
  • f9910d6094 Fixing depth parameter in fifo Andreas Olofsson 2016-04-14 15:54:23 -04:00
  • b70b9de811 Merge pull request #65 from olajep/vivado-localparam-clog2-fix Andreas Olofsson 2016-04-14 15:53:35 -04:00
  • 305c63c911 Merge pull request #64 from olajep/merge-stable Andreas Olofsson 2016-04-14 15:53:19 -04:00
  • 62469afc4b Vivado doesn't like localparam / clog2 combo Ola Jeppsson 2016-04-14 21:46:14 +02:00
  • 652f928377 Merge branch 'stable-prepared' into merge-stable Ola Jeppsson 2016-04-14 20:40:03 +02:00
  • 4c9f3273b1 Move parallella to src/ Ola Jeppsson 2016-04-14 20:30:46 +02:00
  • 8171b9023a src/parallella/fpga: Rename headless to headless_e16_z7020 Ola Jeppsson 2016-04-14 20:26:34 +02:00
  • 6b72eab0fe Merge pull request #63 from olajep/e16-z7010-headless stable Andreas Olofsson 2016-04-14 13:52:42 -04:00
  • e66c526fec Merge pull request #62 from olajep/gpio-driver Andreas Olofsson 2016-04-14 13:00:48 -04:00
  • dccfe3d0b4 GPIO: Remove direction cache variable Ola Jeppsson 2016-04-14 18:57:31 +02:00
  • 8faa91bc52 Instantiating oh_memory_ram in dp/sp memories Andreas Olofsson 2016-04-14 10:30:19 -04:00
  • 709f91c306 Using DEPTH as specifier for memory - More natural design interface (than AW) Andreas Olofsson 2016-04-14 10:29:49 -04:00
  • a08b5d55b5 Adding generic RAM module - one read, one write port - needed something simpler for modeling, maximuze code reuse - _sp/_dp are really there so that you can build designs that will abstract away chip/fpga details Andreas Olofsson 2016-04-14 10:28:30 -04:00
  • d730e46e0b Fixing oh_dsync instantiation - to add new reset pin (can be tied to 1'b1 sometimes) Andreas Olofsson 2016-04-13 20:54:12 -04:00
  • 70340040ce Fixing killer bugs in async fifo! - Adding reset on dsync (sometimes there is no clock) - Separated reset for wr/rd - One of the sync clocks was wrong (found by review) Andreas Olofsson 2016-04-13 20:50:48 -04:00
  • 42c7f4ed0d Improving dsync - adding ability to drive random delay values on each bit in multibit sync - adding async reset (need was found during integration testing) Andreas Olofsson 2016-04-13 20:48:37 -04:00
  • a6e1b22f9f Adding async reset to debuncer. - Can't guarantee that there will be a clock at startup. - All IO modules with suspect clocking situation should have async reset on all key signals. - To test, then you turn off clock and look for "x propagation". Andreas Olofsson 2016-04-13 20:47:22 -04:00
  • 0432f22c67 Simplifyinf bin2gray interface - Using gray/bin as inputs was cute, but not useful when actually instantiating and reading the code. in/out works better. Andreas Olofsson 2016-04-13 20:46:02 -04:00
  • 3ccd72016e Merge pull request #61 from olajep/gpio-driver Andreas Olofsson 2016-04-13 09:56:37 -04:00
  • 510b6669a8 GPIO: Add raw register access API Ola Jeppsson 2016-04-13 15:31:47 +02:00
  • 137994f13a GPIO: Drop "oh" prefix in file names and API Ola Jeppsson 2016-04-13 15:30:16 +02:00
  • ff7018b4ac Making all significant GPIO registers readable for now - Would really prefer if this could be handled in the driver.. Andreas Olofsson 2016-04-13 09:02:30 -04:00
  • 33f3af9f79 Making GPIO_DIR readable Andreas Olofsson 2016-04-13 09:00:24 -04:00
  • f22b833908 GPIO: Add GPIO driver Ola Jeppsson 2016-04-13 13:16:14 +02:00
  • 94b73eb2d0 GPIO: Remove old driver template Ola Jeppsson 2016-04-13 13:11:13 +02:00
  • 543bde926b GPIO: Add DIRIN and DIROUT registers Ola Jeppsson 2016-04-13 11:53:07 +02:00
  • 30555c5375 Adding nreset to command reg - Not 100% sure on this. Ideally I think you would want the ss signal to be the "reset" of all this logic, but the command register gets too tricky. - Is there an issue in having a async active low reset pin on the this interface. Considering that this is only a problem for the remote fetch logic (which will definitely have a nreset signal) I think this is ok... Andreas Olofsson 2016-04-12 09:42:52 -04:00
  • 24957b73d3 Making interrupt 0 non-maskable. Andreas Olofsson 2016-04-11 20:36:58 -04:00
  • e6ed2f2855 Cleanup register addresses of PIC Andreas Olofsson 2016-04-11 20:32:42 -04:00
  • 6c0ce1ff00 Adding README for PIC Andreas Olofsson 2016-04-11 20:31:30 -04:00
  • 191f3b4db8 Fixing gpio initial use case example Andreas Olofsson 2016-04-11 19:27:23 -04:00
  • 7ab30d9f9b Initial thoughts on a gpio driver Andreas Olofsson 2016-04-11 15:46:54 -04:00
  • 101fb7de66 Copyright transfer - All OH! code transferred from Adapteva to non-profit Parallella Foundation Andreas Olofsson 2016-04-11 12:05:29 -04:00
  • 1a790eaf24 Preparing for safer clock setting changes Andreas Olofsson 2016-04-11 12:04:30 -04:00
  • f25aa0ff45 Cleanup after common lib refactoring - clockdiv takes no parameter Andreas Olofsson 2016-04-11 12:03:44 -04:00
  • 2688bc5aa4 Refactoring common library - Updating interfaces to 2005 style - Adding license pointers to all files Andreas Olofsson 2016-04-11 12:01:59 -04:00
  • 5b8328826e Making rsync interface scalar - Who ever uses a vectorized reset.... (if you do, use generate...) Andreas Olofsson 2016-04-11 11:59:18 -04:00
  • fef2bdbe08 Making latch interface generic - Should look like a standard cell gate Andreas Olofsson 2016-04-11 11:58:54 -04:00
  • 5304fd2df2 Fixing compilation errors Andreas Olofsson 2016-04-11 11:13:08 -04:00
  • 01a74a3db9 Removing ce from oddr - Better to turn off clock if you want to save power - The CE was actually increasing the power by N x by making every data signal a clock :-) Andreas Olofsson 2016-04-11 10:30:02 -04:00
  • f62d7c0975 Vectorizing csa modules Andreas Olofsson 2016-04-11 09:34:57 -04:00
  • d2fbbcf341 Enhancing GPIO block - implementing interrupt handling - edge/level support - moving to single register for "DIR", avoids confusion - adding ILATCLR for clearing interrupts - changing to N parameter away from clumsy 64 bit chunk - if you want longer GPIO, instantiate more vectors - up to N==AW supported by this model - trying out more modern Verilog features Andreas Olofsson 2016-04-10 23:24:26 -04:00
  • 233a4150dd Fixing remote fetch spi feature - Added missing reset - Using rising edge of ss (after nreset deasserted) as indicator (and command reg is set to fetch) - Seems like it should be robust across all clk/sclk frequencies. Can use ss high pause to control timing. -Assumption, reset is asserted until ss has settled on to "high" at powerup...seems like this is a must not just for fetch. Andreas Olofsson 2016-04-10 20:56:28 -04:00
  • e22a32853b Merge branch 'master' of github.com:parallella/oh Andreas Olofsson 2016-04-07 19:08:44 -04:00
  • 7fc5d7da1c Cleanin up wait signal -There were some corner case problems when driving non safe interfaces like the SPI...can't always have the luxuary of a fifo Andreas Olofsson 2016-04-07 19:07:44 -04:00
  • f610a31d42 Cleanup spi readme Andreas Olofsson 2016-04-07 19:05:01 -04:00
  • 534f847592 Adding SPI examples Andreas Olofsson 2016-04-07 19:03:11 -04:00
  • dd238b5356 SPI now with working emesh packet transfers working - (see test_basic.emf for example) - basically works by pushing consecutive bytes into FIFO (104 bits) - need to make sure the FIFO does not go empty Andreas Olofsson 2016-04-07 18:46:26 -04:00
  • f5104a62ea Launching data on falling edge on default spi mode (as it should be...not sure how I missed this) Andreas Olofsson 2016-04-07 18:44:41 -04:00
  • f1babdb680 Fixing spi master pushback bug Andreas Olofsson 2016-04-07 18:44:24 -04:00
  • 952657dbd5 Reomving redundant emode feature from spi Andreas Olofsson 2016-04-07 18:44:05 -04:00
  • 0a1690de94 Fixing epiphany spi fetch - adding a separate serializer for the remote fetch (cleaner) - fixing the load signal to load on all bytes while ss low - removing reset from command register - review sync for spi...feels ok to use the rising edge of ss to sync to clock (note, there must be a free running clk for remote fetch) - adding wait pushback on remote fetch Andreas Olofsson 2016-04-07 18:39:39 -04:00
  • 42649ef2c1 SPI slave fixup - removing emode (was redundant) - fixing user regs issue - adding status bit to poll for returned data on fetch Andreas Olofsson 2016-04-07 18:38:29 -04:00
  • 542fec92e9 Completing test for "epiphany" remote read over spi Andreas Olofsson 2016-04-07 18:37:39 -04:00
  • ea3c38e189 Adding shutdown signal for macro - Needed for proper power management, should not be lumped with config Andreas Olofsson 2016-04-06 11:53:03 -04:00
  • 1b512cdbde Removing asic config dependancy - No plans for dual ported memory use for now, if this changes and there needs to be differentiation, then this should probably be a parameter rather than define. (since you might want to choose between regs based and macro based depending on size of memory). Andreas Olofsson 2016-04-06 11:51:03 -04:00
  • 83c3caf1c4 Adding back resets - Was a little overzealous removing resets in module. Note that these problems popped in recently, were no in the original silicon. Andreas Olofsson 2016-04-06 11:50:09 -04:00
  • 8c224d6771 Fixing memory macro instantiation - too many variations (polarity etc) on memory interface, stay with generics (repair + config) - hookup magic happens under the hood Andreas Olofsson 2016-04-05 22:43:29 -04:00
  • 1c1a4dae66 Merge branch 'master' of github.com:parallella/oh Andreas Olofsson 2016-04-05 16:10:50 -04:00
  • 2bc7c82271 Driving realistic power ramp in startup Andreas Olofsson 2016-04-05 16:10:25 -04:00
  • 65a888963c Fixing power buffer model Andreas Olofsson 2016-04-05 16:09:20 -04:00
  • ae98be160e Implementing basic model checking for shutdown logic Andreas Olofsson 2016-04-05 16:08:33 -04:00
  • 9e57e4c3fd Update README.md Andreas Olofsson 2016-04-04 14:55:55 -04:00
  • ff5e5eff5b Fixing basic bug -Vector input not accounted for Andreas Olofsson 2016-04-04 13:37:50 -04:00
  • 1c4309160f Changing parameter for emesh_if -Only one to keep track of (AW) Andreas Olofsson 2016-04-04 13:35:49 -04:00
  • 88a743d5a1 Adding design guideline - Circuit level blocks/hacks should be separate from logic with interface Andreas Olofsson 2016-04-04 13:34:48 -04:00
  • a71caf2f42 Removing confusing names on signals - The c2io, io2c should never be inside the module! - Use in/out to clarify direction in interface modules - The signal direction is indicated at the connectoin level (wrapper)...final decision.... Andreas Olofsson 2016-04-04 09:00:38 -04:00
  • 822bfcbecc Fixing interface for power gate Andreas Olofsson 2016-04-02 22:39:37 -04:00
  • 93e7e5dbab Changing parameter default to 1 - Ease of use, not manditory to override default for N=1 Andreas Olofsson 2016-04-01 22:57:12 -04:00
  • 53e11ec300 Fixing dut_spi interface - adding hw_en - removing mastermode from interface, not needed Andreas Olofsson 2016-04-01 10:07:01 -04:00
  • 43b3c32381 Removing DMA from logic Andreas Olofsson 2016-04-01 10:06:28 -04:00
  • 2263592940 Reorg Andreas Olofsson 2016-03-31 23:06:43 -04:00
  • 1dc41b79e6 Adding power supply pins to dma (place holder) Andreas Olofsson 2016-03-31 23:05:05 -04:00