adapteva.com Adapteva ecfg_split 1.0 mcfg0 sw_reset mcfg0_sw_reset tx_enable mcfg0_tx_enable tx_mmu_mode mcfg0_tx_mmu_mode tx_gpio_mode mcfg0_tx_gpio_mode tx_ctrl_mode mcfg0_tx_ctrl_mode tx_clkdiv mcfg0_tx_clkdiv rx_enable mcfg0_rx_enable rx_mmu_mode mcfg0_rx_mmu_mode rx_gpio_mode mcfg0_rx_gpio_mode rx_loopback_mode mcfg0_rx_loopback_mode coreid mcfg0_coreid datain mcfg0_datain dataout mcfg0_dataout mcfg1 sw_reset mcfg1_sw_reset tx_enable mcfg1_tx_enable tx_mmu_mode mcfg1_tx_mmu_mode tx_gpio_mode mcfg1_tx_gpio_mode tx_ctrl_mode mcfg1_tx_ctrl_mode tx_clkdiv mcfg1_tx_clkdiv rx_enable mcfg1_rx_enable rx_mmu_mode mcfg1_rx_mmu_mode rx_gpio_mode mcfg1_rx_gpio_mode rx_loopback_mode mcfg1_rx_loopback_mode coreid mcfg1_coreid datain mcfg1_datain dataout mcfg1_dataout mcfg2 sw_reset mcfg2_sw_reset tx_enable mcfg2_tx_enable tx_mmu_mode mcfg2_tx_mmu_mode tx_gpio_mode mcfg2_tx_gpio_mode tx_ctrl_mode mcfg2_tx_ctrl_mode tx_clkdiv mcfg2_tx_clkdiv rx_enable mcfg2_rx_enable rx_mmu_mode mcfg2_rx_mmu_mode rx_gpio_mode mcfg2_rx_gpio_mode rx_loopback_mode mcfg2_rx_loopback_mode coreid mcfg2_coreid datain mcfg2_datain dataout mcfg2_dataout mcfg3 sw_reset mcfg3_sw_reset tx_enable mcfg3_tx_enable tx_mmu_mode mcfg3_tx_mmu_mode tx_gpio_mode mcfg3_tx_gpio_mode tx_ctrl_mode mcfg3_tx_ctrl_mode tx_clkdiv mcfg3_tx_clkdiv rx_enable mcfg3_rx_enable rx_mmu_mode mcfg3_rx_mmu_mode rx_gpio_mode mcfg3_rx_gpio_mode rx_loopback_mode mcfg3_rx_loopback_mode coreid mcfg3_coreid datain mcfg3_datain dataout mcfg3_dataout mcfg4 sw_reset mcfg4_sw_reset tx_enable mcfg4_tx_enable tx_mmu_mode mcfg4_tx_mmu_mode tx_gpio_mode mcfg4_tx_gpio_mode tx_ctrl_mode mcfg4_tx_ctrl_mode tx_clkdiv mcfg4_tx_clkdiv rx_enable mcfg4_rx_enable rx_mmu_mode mcfg4_rx_mmu_mode rx_gpio_mode mcfg4_rx_gpio_mode rx_loopback_mode mcfg4_rx_loopback_mode coreid mcfg4_coreid datain mcfg4_datain dataout mcfg4_dataout slvcfg sw_reset slvcfg_sw_reset tx_enable slvcfg_tx_enable tx_mmu_mode slvcfg_tx_mmu_mode tx_gpio_mode slvcfg_tx_gpio_mode tx_ctrl_mode slvcfg_tx_ctrl_mode tx_clkdiv slvcfg_tx_clkdiv rx_enable slvcfg_rx_enable rx_mmu_mode slvcfg_rx_mmu_mode rx_gpio_mode slvcfg_rx_gpio_mode rx_loopback_mode slvcfg_rx_loopback_mode coreid slvcfg_coreid datain slvcfg_datain dataout slvcfg_dataout xilinx_verilogsynthesis Verilog Synthesis verilogSource:vivado.xilinx.com:synthesis verilog ecfg_split xilinx_verilogsynthesis_view_fileset viewChecksum 47bd32f7 xilinx_verilogbehavioralsimulation Verilog Simulation verilogSource:vivado.xilinx.com:simulation verilog ecfg_split xilinx_verilogbehavioralsimulation_view_fileset viewChecksum 47bd32f7 xilinx_xpgui UI Layout :vivado.xilinx.com:xgui.ui xilinx_xpgui_view_fileset viewChecksum e65e5adf slvcfg_datain out 10 0 std_logic_vector xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation mcfg0_sw_reset out std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation mcfg0_tx_enable out std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation mcfg0_tx_mmu_mode out std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation mcfg0_tx_gpio_mode out std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation mcfg0_tx_ctrl_mode out 3 0 std_logic_vector xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation mcfg0_tx_clkdiv out 3 0 std_logic_vector xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation mcfg0_rx_enable out std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation mcfg0_rx_mmu_mode out std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation mcfg0_rx_gpio_mode out std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation mcfg0_rx_loopback_mode out std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation mcfg0_coreid out 11 0 std_logic_vector xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation mcfg0_dataout out 10 0 std_logic_vector xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation mcfg1_sw_reset out std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation mcfg1_tx_enable out std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation mcfg1_tx_mmu_mode out std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation mcfg1_tx_gpio_mode out std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation mcfg1_tx_ctrl_mode out 3 0 std_logic_vector xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation mcfg1_tx_clkdiv out 3 0 std_logic_vector xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation mcfg1_rx_enable out std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation mcfg1_rx_mmu_mode out std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation mcfg1_rx_gpio_mode out std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation mcfg1_rx_loopback_mode out std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation mcfg1_coreid out 11 0 std_logic_vector xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation mcfg1_dataout out 10 0 std_logic_vector xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation mcfg2_sw_reset out std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation mcfg2_tx_enable out std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation mcfg2_tx_mmu_mode out std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation mcfg2_tx_gpio_mode out std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation mcfg2_tx_ctrl_mode out 3 0 std_logic_vector xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation mcfg2_tx_clkdiv out 3 0 std_logic_vector xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation mcfg2_rx_enable out std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation mcfg2_rx_mmu_mode out std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation mcfg2_rx_gpio_mode out std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation mcfg2_rx_loopback_mode out std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation mcfg2_coreid out 11 0 std_logic_vector xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation mcfg2_dataout out 10 0 std_logic_vector xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation mcfg3_sw_reset out std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation mcfg3_tx_enable out std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation mcfg3_tx_mmu_mode out std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation mcfg3_tx_gpio_mode out std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation mcfg3_tx_ctrl_mode out 3 0 std_logic_vector xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation mcfg3_tx_clkdiv out 3 0 std_logic_vector xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation mcfg3_rx_enable out std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation mcfg3_rx_mmu_mode out std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation mcfg3_rx_gpio_mode out std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation mcfg3_rx_loopback_mode out std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation mcfg3_coreid out 11 0 std_logic_vector xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation mcfg3_dataout out 10 0 std_logic_vector xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation mcfg4_sw_reset out std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation mcfg4_tx_enable out std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation mcfg4_tx_mmu_mode out std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation mcfg4_tx_gpio_mode out std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation mcfg4_tx_ctrl_mode out 3 0 std_logic_vector xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation mcfg4_tx_clkdiv out 3 0 std_logic_vector xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation mcfg4_rx_enable out std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation mcfg4_rx_mmu_mode out std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation mcfg4_rx_gpio_mode out std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation mcfg4_rx_loopback_mode out std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation mcfg4_coreid out 11 0 std_logic_vector xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation mcfg4_dataout out 10 0 std_logic_vector xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation slvcfg_sw_reset in std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation slvcfg_tx_enable in std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation slvcfg_tx_mmu_mode in std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation slvcfg_tx_gpio_mode in std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation slvcfg_tx_ctrl_mode in 3 0 std_logic_vector xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation slvcfg_tx_clkdiv in 3 0 std_logic_vector xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation slvcfg_rx_enable in std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation slvcfg_rx_mmu_mode in std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation slvcfg_rx_gpio_mode in std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation slvcfg_rx_loopback_mode in std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation slvcfg_coreid in 11 0 std_logic_vector xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation slvcfg_dataout in 10 0 std_logic_vector xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation mcfg0_datain in 10 0 std_logic_vector xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation 0 mcfg1_datain in 10 0 std_logic_vector xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation 0 mcfg2_datain in 10 0 std_logic_vector xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation 0 mcfg3_datain in 10 0 std_logic_vector xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation 0 mcfg4_datain in 10 0 std_logic_vector xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation 0 choices_0 ACTIVE_HIGH ACTIVE_LOW choices_1 ACTIVE_HIGH ACTIVE_LOW choices_2 ACTIVE_HIGH ACTIVE_LOW choices_3 ACTIVE_HIGH ACTIVE_LOW choices_4 ACTIVE_HIGH ACTIVE_LOW xilinx_verilogsynthesis_view_fileset hdl/ecfg_split.v verilogSource IMPORTED_FILE CHECKSUM_47bd32f7 xilinx_verilogbehavioralsimulation_view_fileset hdl/ecfg_split.v verilogSource IMPORTED_FILE xilinx_xpgui_view_fileset xgui/ecfg_split_v1_0.tcl tclSource XGUI_VERSION_2 CHECKSUM_e65e5adf ecfg_split_v1_0 Component_Name Component Name ecfg_split_v1_0 zynq /BaseIP ecfg_split_v1_0 eCfg Bus Splitter http://www.adapteva.com 3 user.org:user:ecfg_split:1.0 2014-11-09T03:43:55Z /mnt/windowsC/Adapteva/Parallella/parallella-hwelink/fpga/src/ecfg_split 2014.3