adapteva.com Adapteva emaxi 1.0 M00_AXI AWID m00_axi_awid AWADDR m00_axi_awaddr AWLEN m00_axi_awlen AWSIZE m00_axi_awsize AWBURST m00_axi_awburst AWLOCK m00_axi_awlock AWCACHE m00_axi_awcache AWPROT m00_axi_awprot AWQOS m00_axi_awqos AWUSER m00_axi_awuser AWVALID m00_axi_awvalid AWREADY m00_axi_awready WDATA m00_axi_wdata WSTRB m00_axi_wstrb WLAST m00_axi_wlast WUSER m00_axi_wuser WVALID m00_axi_wvalid WREADY m00_axi_wready BID m00_axi_bid BRESP m00_axi_bresp BUSER m00_axi_buser BVALID m00_axi_bvalid BREADY m00_axi_bready ARID m00_axi_arid ARADDR m00_axi_araddr ARLEN m00_axi_arlen ARSIZE m00_axi_arsize ARBURST m00_axi_arburst ARLOCK m00_axi_arlock ARCACHE m00_axi_arcache ARPROT m00_axi_arprot ARQOS m00_axi_arqos ARUSER m00_axi_aruser ARVALID m00_axi_arvalid ARREADY m00_axi_arready RID m00_axi_rid RDATA m00_axi_rdata RRESP m00_axi_rresp RLAST m00_axi_rlast RUSER m00_axi_ruser RVALID m00_axi_rvalid RREADY m00_axi_rready WIZ.DATA_WIDTH 32 SUPPORTS_NARROW_BURST 0 M00_AXI_RST RST m00_axi_aresetn POLARITY ACTIVE_LOW M00_AXI_CLK CLK m00_axi_aclk ASSOCIATED_BUSIF M00_AXI ASSOCIATED_RESET m00_axi_aresetn emrr WR_DATA emrr_wr_data WR_EN emrr_wr_en FULL emrr_full emrq RD_DATA emrq_rd_data RD_EN emrq_rd_en EMPTY emrq_empty emwr RD_DATA emwr_rd_data RD_EN emwr_rd_en EMPTY emwr_empty M00_AXI 4294967296 64 xilinx_verilogsynthesis Verilog Synthesis verilogSource:vivado.xilinx.com:synthesis verilog emaxi_v1_0 xilinx_verilogsynthesis_view_fileset viewChecksum fe4bbe14 xilinx_verilogbehavioralsimulation Verilog Simulation verilogSource:vivado.xilinx.com:simulation verilog emaxi_v1_0 xilinx_verilogbehavioralsimulation_view_fileset viewChecksum fe4bbe14 xilinx_xpgui UI Layout :vivado.xilinx.com:xgui.ui xilinx_xpgui_view_fileset viewChecksum f0c27c1c bd_tcl Block Diagram :vivado.xilinx.com:block.diagram bd_tcl_view_fileset viewChecksum 45a2f450 emwr_rd_data in 102 0 wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation 0 emwr_rd_en out wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation emwr_empty in wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation 1 emrq_rd_data in 102 0 wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation 0 emrq_rd_en out wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation emrq_empty in wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation 1 emrr_wr_data out 102 0 wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation emrr_wr_en out wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation emrr_full in wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation 0 emrr_prog_full in wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation 0 m00_axi_awid out 0 0 wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation 0 optional true m00_axi_awaddr out 31 0 wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation m00_axi_awlen out 7 0 wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation m00_axi_awsize out 2 0 wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation m00_axi_awburst out 1 0 wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation m00_axi_awlock out wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation m00_axi_awcache out 3 0 wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation m00_axi_awprot out 2 0 wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation m00_axi_awqos out 3 0 wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation m00_axi_awuser out 0 0 wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation 0 optional false m00_axi_awvalid out wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation m00_axi_awready in wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation m00_axi_wdata out 63 0 wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation m00_axi_wstrb out 7 0 wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation m00_axi_wlast out wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation m00_axi_wuser out 0 0 wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation 0 optional false m00_axi_wvalid out wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation m00_axi_wready in wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation m00_axi_bid in 0 0 wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation 0 optional true m00_axi_bresp in 1 0 wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation m00_axi_buser in 0 0 wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation 0 optional false m00_axi_bvalid in wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation m00_axi_bready out wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation m00_axi_arid out 0 0 wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation 0 optional true m00_axi_araddr out 31 0 wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation m00_axi_arlen out 7 0 wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation m00_axi_arsize out 2 0 wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation m00_axi_arburst out 1 0 wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation m00_axi_arlock out wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation m00_axi_arcache out 3 0 wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation m00_axi_arprot out 2 0 wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation m00_axi_arqos out 3 0 wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation m00_axi_aruser out 0 0 wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation 0 optional false m00_axi_arvalid out wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation m00_axi_arready in wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation m00_axi_rid in 0 0 wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation 0 optional true m00_axi_rdata in 63 0 wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation m00_axi_rresp in 1 0 wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation m00_axi_rlast in wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation m00_axi_ruser in 0 0 wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation 0 optional false m00_axi_rvalid in wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation m00_axi_rready out wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation m00_axi_aclk in wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation m00_axi_aresetn in wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation C_M00_AXI_TARGET_SLAVE_BASE_ADDR C_M00_AXI_TARGET_SLAVE_BASE_ADDR Base address of targeted slave 0x40000000 C_M00_AXI_BURST_LEN C_M00_AXI_BURST_LEN Burst Length. Supports 1, 2, 4, 8, 16, 32, 64, 128, 256 burst lengths 16 C_M00_AXI_ID_WIDTH C_M00_AXI_ID_WIDTH Thread ID Width 1 C_M00_AXI_ADDR_WIDTH C_M00_AXI_ADDR_WIDTH Width of Address Bus 32 C_M00_AXI_DATA_WIDTH C_M00_AXI_DATA_WIDTH Width of Data Bus 64 false C_M00_AXI_AWUSER_WIDTH C_M00_AXI_AWUSER_WIDTH Width of User Write Address Bus 1 C_M00_AXI_ARUSER_WIDTH C_M00_AXI_ARUSER_WIDTH Width of User Read Address Bus 1 C_M00_AXI_WUSER_WIDTH C_M00_AXI_WUSER_WIDTH Width of User Write Data Bus 1 C_M00_AXI_RUSER_WIDTH C_M00_AXI_RUSER_WIDTH Width of User Read Data Bus 1 C_M00_AXI_BUSER_WIDTH C_M00_AXI_BUSER_WIDTH Width of User Response Bus 1 choices_0 32 choices_1 1 0 choices_2 1 2 4 8 16 32 64 128 256 choices_3 1 2 4 8 16 32 64 128 256 choices_4 32 64 xilinx_verilogsynthesis_view_fileset hdl/emaxi_v1_0_M00_AXI.v verilogSource hdl/emaxi_v1_0.v verilogSource CHECKSUM_6710a1ec hdl/syncfifo.v verilogSource CHECKSUM_65374fe8 xil_defaultlib xilinx_verilogbehavioralsimulation_view_fileset hdl/emaxi_v1_0_M00_AXI.v verilogSource hdl/emaxi_v1_0.v verilogSource hdl/syncfifo.v verilogSource xil_defaultlib xilinx_xpgui_view_fileset xgui/emaxi_v1_0.tcl tclSource XGUI_VERSION_2 CHECKSUM_f0c27c1c bd_tcl_view_fileset bd/bd.tcl tclSource eLink Master AXI C_M00_AXI_TARGET_SLAVE_BASE_ADDR C M00 AXI TARGET SLAVE BASE ADDR Base address of targeted slave 0x40000000 C_M00_AXI_BURST_LEN C M00 AXI BURST LEN Burst Length. Supports 1, 2, 4, 8, 16, 32, 64, 128, 256 burst lengths 16 C_M00_AXI_ID_WIDTH C M00 AXI ID WIDTH Thread ID Width 1 C_M00_AXI_ADDR_WIDTH C M00 AXI ADDR WIDTH Width of Address Bus 32 false C_M00_AXI_DATA_WIDTH C M00 AXI DATA WIDTH Width of Data Bus 64 false C_M00_AXI_AWUSER_WIDTH C M00 AXI AWUSER WIDTH Width of User Write Address Bus 0 C_M00_AXI_ARUSER_WIDTH C M00 AXI ARUSER WIDTH Width of User Read Address Bus 0 C_M00_AXI_WUSER_WIDTH C M00 AXI WUSER WIDTH Width of User Write Data Bus 0 C_M00_AXI_RUSER_WIDTH C M00 AXI RUSER WIDTH Width of User Read Data Bus 0 C_M00_AXI_BUSER_WIDTH C M00 AXI BUSER WIDTH Width of User Response Bus 0 Component_Name Component Name emaxi_v1_0 zynq AXI_Peripheral emaxi_v1.0 Adapteva, Inc. http://www.adapteva.com 12 2015-01-14T18:46:03Z /home/frhuettig 2014.3