adapteva.com Adatpeva eproto_tx 1.0 signal_reset RST reset POLARITY ACTIVE_HIGH emtx srcaddr emtx_srcaddr access emtx_access datamode emtx_datamode data emtx_data wr_wait emtx_wr_wait ctrlmode emtx_ctrlmode dstaddr emtx_dstaddr write emtx_write rd_wait emtx_rd_wait xilinx_verilogsynthesis Verilog Synthesis verilogSource:vivado.xilinx.com:synthesis verilog eproto_tx xilinx_verilogsynthesis_view_fileset viewChecksum 6b919726 xilinx_verilogbehavioralsimulation Verilog Simulation verilogSource:vivado.xilinx.com:simulation verilog eproto_tx xilinx_verilogbehavioralsimulation_view_fileset viewChecksum 6b919726 xilinx_xpgui UI Layout :vivado.xilinx.com:xgui.ui xilinx_xpgui_view_fileset viewChecksum e65e5adf emtx_rd_wait out reg xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation emtx_wr_wait out reg xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation emtx_ack out reg xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation txframe_p out 7 0 reg xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation txdata_p out 63 0 reg xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation reset in std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation emtx_access in std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation emtx_write in std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation emtx_datamode in 1 0 std_logic_vector xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation emtx_ctrlmode in 3 0 std_logic_vector xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation emtx_dstaddr in 31 0 std_logic_vector xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation emtx_srcaddr in 31 0 std_logic_vector xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation emtx_data in 31 0 std_logic_vector xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation txlclk_p in std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation tx_rd_wait in std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation tx_wr_wait in std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation choices_0 ACTIVE_HIGH ACTIVE_LOW xilinx_verilogsynthesis_view_fileset hdl/eproto_tx.v verilogSource IMPORTED_FILE CHECKSUM_df6c71d1 xilinx_verilogbehavioralsimulation_view_fileset hdl/eproto_tx.v verilogSource IMPORTED_FILE xilinx_xpgui_view_fileset xgui/eproto_tx_v1_0.tcl tclSource XGUI_VERSION_2 CHECKSUM_e65e5adf eLink TX Protocol Generator Component_Name Component Name eproto_tx_v1_0 zynq /BaseIP eproto_tx_v1_0 Adapteva, Inc. http://www.adapteva.com 3 user.org:user:eproto_tx:1.0 2014-11-15T05:06:01Z /mnt/windowsC/Adapteva/Parallella/parallella-hwelink/fpga/src/eproto_tx/ip /mnt/windowsC/Adapteva/Parallella/parallella-hwelink/fpga/src/eproto_tx/ip /mnt/windowsC/Adapteva/Parallella/parallella-hwelink/fpga/src/eproto_tx/ip 2014.3