adapteva.com Adapteva parallella_gpio_emio 1.0 xilinx_verilogsynthesis Verilog Synthesis verilogSource:vivado.xilinx.com:synthesis verilog parallella_gpio_emio xilinx_verilogsynthesis_view_fileset xilinx_verilogbehavioralsimulation Verilog Simulation verilogSource:vivado.xilinx.com:simulation verilog parallella_gpio_emio xilinx_verilogbehavioralsimulation_view_fileset xilinx_xpgui UI Layout :vivado.xilinx.com:xgui.ui xilinx_xpgui_view_fileset PS_GPIO_I out 63 0 std_logic_vector xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation GPIO_P inout 23 0 std_logic_vector xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation GPIO_N inout 23 0 std_logic_vector xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation PS_GPIO_O in 63 0 std_logic_vector xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation PS_GPIO_T in 63 0 std_logic_vector xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation NUM_GPIO_PAIRS Num Gpio Pairs 24 DIFF_GPIO Diff Gpio 0 NUM_PS_SIGS Num Ps Sigs 64 xilinx_verilogsynthesis_view_fileset hdl/parallella_gpio_emio.v verilogSource CHECKSUM_0bb67d45 xilinx_verilogbehavioralsimulation_view_fileset hdl/parallella_gpio_emio.v verilogSource xilinx_xpgui_view_fileset xgui/parallella_gpio_emio_v1_0.tcl tclSource XGUI_VERSION_2 CHECKSUM_47615418 GPIO Implementation for Parallella DIFF_GPIO DIFF_GPIO Set Differential (1) or Single-ended (0) GPIOs 0 NUM_GPIO_PAIRS NUM_GPIO_PAIRS Number of GPIO pairs P/N, or HALF the # of single-ended signals 24 Component_Name Component Name parallella_gpio_emio_v1_0 NUM_PS_SIGS NUM_PS_SIGS Number of PS GPIO signals connected. 64 zynq /Adapteva parallella_gpio_emio_v1_0 Adapteva, Inc. http://www.adapteva.com 3 2015-01-12T21:08:53Z /mnt/windowsC/Adapteva/Parallella/parallella-hwelink/fpga/src/gpio /mnt/windowsC/Adapteva/Parallella/parallella-hwelink/fpga/src/gpio /mnt/windowsC/Adapteva/Parallella/parallella-hwelink/fpga/src/gpio 2014.3