adapteva.com Adapteva edistrib 1.0 ecfg rx_enable ecfg_rx_enable rx_mmu_mode ecfg_rx_mmu_mode ems_dir access ems_dir_access write ems_dir_write datamode ems_dir_datamode ctrlmode ems_dir_ctrlmode dstaddr ems_dir_dstaddr srcaddr ems_dir_srcaddr data ems_dir_data wr_wait ems_dir_wr_wait rd_wait ems_dir_rd_wait ems_mmu access ems_mmu_access write ems_mmu_write datamode ems_mmu_datamode ctrlmode ems_mmu_ctrlmode dstaddr ems_mmu_dstaddr srcaddr ems_mmu_srcaddr data ems_mmu_data emrq WR_DATA emrq_wr_data WR_EN emrq_wr_en FULL emrq_full emrr WR_DATA emrr_wr_data WR_EN emrr_wr_en FULL emrr_full emwr WR_DATA emwr_wr_data WR_EN emwr_wr_en FULL emwr_full xilinx_verilogsynthesis Verilog Synthesis verilogSource:vivado.xilinx.com:synthesis verilog edistrib xilinx_verilogsynthesis_view_fileset viewChecksum e946090b xilinx_verilogbehavioralsimulation Verilog Simulation verilogSource:vivado.xilinx.com:simulation verilog edistrib xilinx_verilogbehavioralsimulation_view_fileset viewChecksum e946090b xilinx_xpgui UI Layout :vivado.xilinx.com:xgui.ui xilinx_xpgui_view_fileset viewChecksum a3cdbfc0 ems_dir_rd_wait out std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation ems_dir_wr_wait out std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation emwr_wr_data out 102 0 wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation 0 emwr_wr_en out reg xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation emrq_wr_data out 102 0 wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation 0 emrq_wr_en out reg xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation emrr_wr_data out 102 0 wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation 0 emrr_wr_en out reg xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation rxlclk in std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation ems_dir_access in std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation ems_dir_write in std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation ems_dir_datamode in 1 0 std_logic_vector xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation ems_dir_ctrlmode in 3 0 std_logic_vector xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation ems_dir_dstaddr in 31 0 std_logic_vector xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation ems_dir_srcaddr in 31 0 std_logic_vector xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation ems_dir_data in 31 0 std_logic_vector xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation ems_mmu_access in std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation ems_mmu_write in std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation ems_mmu_datamode in 1 0 std_logic_vector xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation ems_mmu_ctrlmode in 3 0 std_logic_vector xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation ems_mmu_dstaddr in 31 0 std_logic_vector xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation ems_mmu_srcaddr in 31 0 std_logic_vector xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation ems_mmu_data in 31 0 std_logic_vector xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation emwr_full in std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation 0 emwr_prog_full in std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation 0 emrq_full in std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation 0 emrq_prog_full in std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation 0 emrr_full in std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation 0 emrr_prog_full in std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation 0 ecfg_rx_enable in std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation ecfg_rx_mmu_mode in std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation C_READ_TAG_ADDR C Read Tag Addr 0x810 xilinx_verilogsynthesis_view_fileset hdl/edistrib.v verilogSource IMPORTED_FILE CHECKSUM_61486761 xilinx_verilogbehavioralsimulation_view_fileset hdl/edistrib.v verilogSource IMPORTED_FILE xilinx_xpgui_view_fileset xgui/edistrib_v1_0.tcl tclSource XGUI_VERSION_2 CHECKSUM_a3cdbfc0 eMesh R/W/RR Distributor Component_Name Component Name edistrib_v1_0 C_READ_TAG_ADDR C_READ_TAG_ADDR 0x810 zynq /BaseIP edistrib_v1_0 Adapteva, Inc. http://www.adapteva.com 4 user.org:user:edistrib:1.0 2014-11-16T07:53:22Z /mnt/windowsC/Adapteva/Parallella/parallella-hwelink/fpga/src/edistrib/ip /mnt/windowsC/Adapteva/Parallella/parallella-hwelink/fpga/src/edistrib/ip /mnt/windowsC/Adapteva/Parallella/parallella-hwelink/fpga/src/edistrib/ip 2014.3