adapteva.com Adapteva eCfg 1.0 signal_reset RST reset POLARITY ACTIVE_HIGH ecfg_cclk div ecfg_cclk_div pllcfg ecfg_cclk_pllcfg en ecfg_cclk_en ecfg sw_reset ecfg_sw_reset tx_enable ecfg_tx_enable tx_mmu_mode ecfg_tx_mmu_mode tx_gpio_mode ecfg_tx_gpio_mode tx_ctrl_mode ecfg_tx_ctrl_mode tx_clkdiv ecfg_tx_clkdiv rx_enable ecfg_rx_enable rx_mmu_mode ecfg_rx_mmu_mode rx_gpio_mode ecfg_rx_gpio_mode rx_loopback_mode ecfg_rx_loopback_mode coreid ecfg_coreid datain ecfg_datain dataout ecfg_dataout mi EN mi_en DOUT mi_dout DIN mi_din WE mi_we ADDR mi_addr CLK mi_clk RST mi_rst xilinx_verilogsynthesis Verilog Synthesis verilogSource:vivado.xilinx.com:synthesis verilog ecfg xilinx_verilogsynthesis_view_fileset viewChecksum d52c2edc xilinx_verilogbehavioralsimulation Verilog Simulation verilogSource:vivado.xilinx.com:simulation verilog ecfg xilinx_verilogbehavioralsimulation_view_fileset viewChecksum d52c2edc xilinx_xpgui UI Layout :vivado.xilinx.com:xgui.ui xilinx_xpgui_view_fileset viewChecksum cab9d07b mi_dout out 31 0 reg xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation ecfg_sw_reset out std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation ecfg_tx_enable out std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation ecfg_tx_mmu_mode out std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation ecfg_tx_gpio_mode out std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation ecfg_tx_ctrl_mode out 3 0 std_logic_vector xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation ecfg_tx_clkdiv out 3 0 std_logic_vector xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation ecfg_rx_enable out std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation ecfg_rx_mmu_mode out std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation ecfg_rx_gpio_mode out std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation ecfg_rx_loopback_mode out std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation ecfg_cclk_en out std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation ecfg_cclk_div out 3 0 std_logic_vector xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation ecfg_cclk_pllcfg out 3 0 std_logic_vector xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation ecfg_coreid out 11 0 std_logic_vector xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation ecfg_dataout out 10 0 std_logic_vector xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation param_coreid in 11 0 std_logic_vector xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation mi_clk in std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation mi_rst in std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation reset in std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation mi_en in std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation mi_we in std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation mi_addr in 11 0 std_logic_vector xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation mi_din in 31 0 std_logic_vector xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation 8 ecfg_datain in 10 0 std_logic_vector xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation E_VERSION E Version 0x00000000 IDW Idw 12 RFAW Rfaw 12 choices_0 ACTIVE_HIGH ACTIVE_LOW choices_1 ACTIVE_HIGH ACTIVE_LOW xilinx_verilogsynthesis_view_fileset hdl/ecfg.v verilogSource CHECKSUM_d52c2edc xilinx_verilogbehavioralsimulation_view_fileset hdl/ecfg.v verilogSource xilinx_xpgui_view_fileset xgui/eCfg_v1_0.tcl tclSource XGUI_VERSION_2 CHECKSUM_cab9d07b eLink Configuration Register RFAW Rfaw 12 IDW Idw 12 E_VERSION E Version 0x00000000 Component_Name Component Name ecfg_v1_0 zynq /BaseIP ecfg_v1_0 eCfg http://www.adapteva.com 5 user.org:user:ecfg:1.0 2014-11-17T20:33:45Z /mnt/windowsC/Adapteva/Parallella/parallella-hwelink/fpga/src/ecfg/ip /mnt/windowsC/Adapteva/Parallella/parallella-hwelink/fpga/src/ecfg/ip /mnt/windowsC/Adapteva/Parallella/parallella-hwelink/fpga/src/ecfg/ip /mnt/windowsC/Adapteva/Parallella/parallella-hwelink/fpga/src/ecfg/ip 2014.3