xilinx.com xci unknown 1.0 fifo_async_104x32 fifo_async_104x32 Independent_Clocks_Distributed_RAM 2 2 Native Standard_FIFO false 104 32 104 32 false false true false Asynchronous_Reset 0 true 0 false true false true Active_High false Active_High false Active_High false Active_High false false false false false 5 false 5 false 5 false 1 1 Single_Programmable_Full_Threshold_Constant 16 15 No_Programmable_Empty_Threshold 2 3 AXI4 Common_Clock false Slave_Interface_Clock_Enable READ_WRITE 0 32 64 0 0 0 0 0 1 0 0 4 true false false 1 false 1 FIFO Common_Clock_Block_RAM Data_FIFO false false false 16 false No_Programmable_Full_Threshold 1023 No_Programmable_Empty_Threshold 1022 FIFO Common_Clock_Block_RAM Data_FIFO false false false 1024 false No_Programmable_Full_Threshold 1023 No_Programmable_Empty_Threshold 1022 FIFO Common_Clock_Block_RAM Data_FIFO false false false 16 false No_Programmable_Full_Threshold 1023 No_Programmable_Empty_Threshold 1022 FIFO Common_Clock_Block_RAM Data_FIFO false false false 16 false No_Programmable_Full_Threshold 1023 No_Programmable_Empty_Threshold 1022 FIFO Common_Clock_Block_RAM Data_FIFO false false false 1024 false No_Programmable_Full_Threshold 1023 No_Programmable_Empty_Threshold 1022 FIFO Common_Clock_Block_RAM Data_FIFO false false false 1024 false No_Programmable_Full_Threshold 1023 No_Programmable_Empty_Threshold 1022 Fully_Registered Fully_Registered Fully_Registered Fully_Registered Fully_Registered Fully_Registered false Active_High false Active_High false false false false false false false false 0 0 5 BlankString 104 0 104 0 zynq 0 0 1 0 0 0 0 0 0 0 1 0 0 1 0 0 0 2 0 2 BlankString 0 0 1 0 512x72 2 3 0 16 15 1 5 32 1 5 0 1 0 0 0 0 0 0 0 0 5 32 1 5 1 1 0 0 2 0 1 1 1 0 0 0 0 0 0 1 32 64 8 1 0 0 0 0 0 0 1 1 1 1 1 1 0 0 1 1 0 0 0 8 1 1 4 1 1 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 512x36 1kx36 512x36 512x36 1kx36 1kx18 0 0 0 0 0 0 0 0 0 0 0 0 32 64 2 32 64 1 16 1024 16 16 1024 1024 4 10 4 4 10 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1023 1023 1023 1023 1023 1023 0 0 0 0 0 0 1022 1022 1022 1022 1022 1022 0 0 0 0 0 0 zynq xc7z020 clg484 -1 C VERILOG MIXED TRUE TRUE em.avnet.com:zed:part0:1.2 TRUE 2014.3.1 2 OUT_OF_CONTEXT . .