adapteva.com Adapteva eclock 1.0 signal_reset RST reset POLARITY ACTIVE_HIGH ecfg_cclk div ecfg_cclk_div pllcfg ecfg_cclk_pllcfg en ecfg_cclk_en xilinx_verilogsynthesis Verilog Synthesis verilogSource:vivado.xilinx.com:synthesis verilog eclock xilinx_verilogsynthesis_view_fileset viewChecksum 4c07ce39 xilinx_verilogbehavioralsimulation Verilog Simulation verilogSource:vivado.xilinx.com:simulation verilog eclock xilinx_verilogbehavioralsimulation_view_fileset viewChecksum 4c07ce39 xilinx_xpgui UI Layout :vivado.xilinx.com:xgui.ui xilinx_xpgui_view_fileset viewChecksum f5b360c1 CCLK_P out std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation CCLK_N out std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation lclk_s out std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation lclk_out out std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation lclk_p out std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation clkin in std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation reset in std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation ecfg_cclk_en in std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation ecfg_cclk_div in 3 0 std_logic_vector xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation ecfg_cclk_pllcfg in 3 0 std_logic_vector xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation CLKIN_PERIOD Clkin Period 10 CLKIN_DIVIDE Clkin Divide 1 VCO_MULT Vco Mult 12 CCLK_DIVIDE Cclk Divide 2 LCLK_DIVIDE Lclk Divide 4 FEATURE_CCLK_DIV Feature Cclk Div "1" IOSTD_ELINK Iostd Elink LVDS_25 choices_0 ACTIVE_HIGH ACTIVE_LOW xilinx_verilogsynthesis_view_fileset hdl/eclock.v verilogSource CHECKSUM_e391c4dc xilinx_verilogbehavioralsimulation_view_fileset hdl/eclock.v verilogSource xilinx_xpgui_view_fileset xgui/eclock_v1_0.tcl tclSource XGUI_VERSION_2 CHECKSUM_f5b360c1 eClock Clock Generation Module IOSTD_ELINK Iostd Elink LVDS_25 FEATURE_CCLK_DIV Feature Cclk Div "1" LCLK_DIVIDE Lclk Divide 4 CCLK_DIVIDE Cclk Divide 2 VCO_MULT Vco Mult 12 CLKIN_DIVIDE Clkin Divide 1 CLKIN_PERIOD Clkin Period 10 Component_Name Component Name eclock_v1_0 zynq /BaseIP eclock_v1_0 Adapteva, Inc. http://www.adapteva.com 7 2014-11-21T16:37:07Z /mnt/windowsC/Adapteva/Parallella/parallella-hwelink/fpga/hdl/eclock/ip /mnt/windowsC/Adapteva/Parallella/parallella-hwelink/fpga/hdl/eclock/ip /home/frhuettig 2014.3