00000000_00000001_800e0000_0b //assert reset 
00000000_00000001_800e0004_0b //clocks on full speed
00000000_00000111_800e0004_0b //clk/2
00000000_00000221_800e0004_0b //clk/4
00000000_00000331_800e0004_0b //clk/8
00000000_00000441_800e0004_0b //clk/16
00000000_00000551_800e0004_0b //clk/32
00000000_00000000_80000000_0b //dummy wait (to see repeating clock)
00000000_00000000_80000000_0b //dummy wait
00000000_00000661_800e0004_0b //clk/64
00000000_00000000_80000000_0b //dummy wait (to see repeating clock)
00000000_00000000_80000000_0b //dummy wait
00000000_00000000_80000000_0b //dummy wait
00000000_00000000_80000000_0b //dummy wait
00000000_00000000_80000000_0b //dummy wait
00000000_00000000_800e0004_0b //stop cclk 
00000000_00000000_800e0000_0b //deassert reset
00000000_00000213_800e0004_0b //start cclk and lclk at max speed
00000000_00000001_800e0008_0b //enable tx
00000000_00000001_800e000C_0b //enable rx
00000000_00000555_800e0010_0b //writing to coreid
00000000_00000555_800e0014_0b //writing to version
00000000_00000555_800e001C_0b //writing to dataout (dummy)
00000000_AAAAAAAA_800e0020_0b //write to embox
00000000_BBBBBBBB_800e0024_0b //write to embox
00000000_CCCCCCCC_800d0000_0b //write to emmurx
00000000_00000000_80800000_0b //write to epiphany
00000000_ABCD0001_80800004_0b //write to epiphany
00000000_ABCD0002_80800008_0b //write to epiphany
00000000_ABCD0003_8080000c_0b //write to epiphany
00000000_ABCD0004_80800010_0b //write to epiphany
00000000_ABCD0005_80800014_0b //write to epiphany
00000000_ABCD0006_80800018_0b //write to epiphany
00000000_ABCD0007_8080001c_0b //write to epiphany
00000000_00000000_800e001C_09 //read from dataout register
00000000_00000000_800e0020_09 //read from embox
00000000_00000000_800e0024_09 //read from embox
00000000_00000000_800c0000_09 //read from emmurx
00000000_00000000_80800000_09 //read from epiphany