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# OH!

An Open Hardware library for Chip and FPGA designers written in Verilog.

## CONTENT

| Module                     | Description                                 |
|----------------------------|---------------------------------------------|
| [accelerator](accelerator) | A simple accelerator tutorial               |
| [common](common)           | Library of generally useful components      |
| [emesh](emesh)             | Emesh interface utility circuits            |
| [elink](elink)             | Point to point LVDS link                    |
| [emailbox](emailbox)       | Simple mailbox with interrupt output        |
| [emmu](emmu)               | Simple memory transaction translation unit  |
| [xilibs](xilibs)           | Simulation modules for Xilinx primitives    |

## LICENSE
The OH! repository source code is licensed under the MIT license unless otherwise specified. See [LICENSE](LICENSE) for MIT copyright terms. Design specific licenses can be found in the folder root (eg: aes/LICENSE) 

## CONTRIBUTING
Instructions for contributing can be found [HERE](CONTRIBUTING.md).

## RECOMMEND TOOLS

* [Verilator Simulator](http://www.veripool.org/wiki/verilator)
* [Emacs Verilog Mode](http://www.veripool.org/wiki/verilog-mode)
* [Icarus Simulator](http://iverilog.icarus.com)
* [GTKWave](http://gtkwave.sourceforge.net)
* [Verilog-Perl](http://www.veripool.org/wiki/verilog-perl)

## RECOMMENDED READING

* [Verilog Quick Reference](verilog/verilog_reference.md)
* [Sunburst Design Verilog Papers](http://www.sunburst-design.com/papers)
* [Sutherland Verilog Papers](http://www.sutherland-hdl.com/papers.html)