xilinx.com xci unknown 1.0 fifo_async_104x32 100000000 100000000 100000000 100000000 100000000 0 0 0 0 0 0 0 8 1 1 1 1 4 0 32 1 1 1 64 1 8 1 1 1 1 0 0 5 BlankString 104 1 32 64 1 64 2 0 104 0 1 0 0 0 0 0 0 0 0 zynquplus 0 0 0 1 0 0 0 0 1 0 1 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 2 1 1 1 1 1 1 0 0 2 BlankString 1 0 0 0 1 0 512x72 1kx18 512x36 512x72 512x36 512x72 512x36 2 1022 1022 1022 1022 1022 1022 3 0 0 0 0 0 0 0 16 1023 1023 1023 1023 1023 1023 15 1 0 0 0 0 0 0 0 0 5 32 1 5 0 0 0 0 0 0 0 2 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 32 1024 16 1024 16 1024 16 1 5 10 4 10 4 10 4 1 32 0 0 false false false 0 0 Slave_Interface_Clock_Enable Common_Clock fifo_async_104x32 64 false 5 false false 0 2 1022 1022 1022 1022 1022 1022 3 false false false false false false false false false Hard_ECC false false false false false false true false false true Data_FIFO Data_FIFO Data_FIFO Data_FIFO Data_FIFO Data_FIFO Common_Clock_Block_RAM Common_Clock_Block_RAM Common_Clock_Block_RAM Common_Clock_Block_RAM Common_Clock_Block_RAM Common_Clock_Block_RAM Independent_Clocks_Distributed_RAM 0 16 1023 1023 1023 1023 1023 1023 15 false false false 0 Native false false false false false false false false false false false false false false 104 32 1024 16 1024 16 1024 16 false 104 32 Embedded_Reg false false Active_High Active_High AXI4 Standard_FIFO No_Programmable_Empty_Threshold No_Programmable_Empty_Threshold No_Programmable_Empty_Threshold No_Programmable_Empty_Threshold No_Programmable_Empty_Threshold No_Programmable_Empty_Threshold No_Programmable_Empty_Threshold Single_Programmable_Full_Threshold_Constant No_Programmable_Full_Threshold No_Programmable_Full_Threshold No_Programmable_Full_Threshold No_Programmable_Full_Threshold No_Programmable_Full_Threshold No_Programmable_Full_Threshold READ_WRITE 0 1 true 5 Fully_Registered Fully_Registered Fully_Registered Fully_Registered Fully_Registered Fully_Registered true Asynchronous_Reset false 1 0 0 1 1 4 false false Active_High Active_High true false false false false Active_High 0 false Active_High 1 false 5 false FIFO false false false false FIFO FIFO 2 2 false FIFO FIFO FIFO zynquplus xczu9eg ffvb1156 VERILOG es2 MIXED -2 I TRUE TRUE IP_Flow 3 TRUE . . 2016.4 OUT_OF_CONTEXT