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289024fd89
- Creating an arbitrary 'src' directory really doesn't help much... - Goal is to make each folder self contained - Make meta repos and individual repos have the same directory structure
77 lines
1.9 KiB
Verilog
77 lines
1.9 KiB
Verilog
//`include "elink_regmap.v"
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module dut(/*AUTOARG*/
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// Outputs
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dut_active, clkout, wait_out, access_out, packet_out,
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// Inputs
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clk1, clk2, nreset, vdd, vss, access_in, packet_in, wait_in
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);
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//##########################################################################
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//# INTERFACE
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//##########################################################################
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parameter AW = 32;
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parameter ID = 12'h810;
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parameter S_IDW = 12;
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parameter M_IDW = 6;
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parameter PW = 2*AW + 40;
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parameter N = 1;
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//clock,reset
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input clk1;
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input clk2;
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input nreset;
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input [N*N-1:0] vdd;
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input vss;
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output dut_active;
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output clkout;
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//Stimulus Driven Transaction
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input [N-1:0] access_in;
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input [N*PW-1:0] packet_in;
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output [N-1:0] wait_out;
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//DUT driven transaction
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output [N-1:0] access_out;
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output [N*PW-1:0] packet_out;
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input [N-1:0] wait_in;
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//##########################################################################
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//#BODY
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//##########################################################################
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wire mem_rd_wait;
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wire mem_wr_wait;
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wire mem_access;
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wire [PW-1:0] mem_packet;
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/*AUTOINPUT*/
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// End of automatics
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/*AUTOWIRE*/
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assign clkout = clk1;
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assign dut_active = 1'b1;
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assign wait_out = 1'b0;
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emailbox emailbox (.reg_rdata (),
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.mailbox_irq (mailbox_irq),
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.mailbox_wait (),
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// Inputs
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.nreset (nreset),
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.wr_clk (clk1),
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.rd_clk (clk1),
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.emesh_access (access_in),
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.emesh_packet (packet_in[PW-1:0]),
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.reg_access (1'b0),
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.reg_packet ({(PW){1'b0}}),
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.mailbox_irq_en (1'b1)
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);
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endmodule
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// Local Variables:
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// verilog-library-directories:("." "../hdl")
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// End:
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