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- Creating an arbitrary 'src' directory really doesn't help much... - Goal is to make each folder self contained - Make meta repos and individual repos have the same directory structure
103 lines
2.6 KiB
Verilog
103 lines
2.6 KiB
Verilog
//Byte Mode:
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//ADDR[2:0] B7 B6 B5 B4 B3 B2 B1 B0
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//x00 0 0 0 MB0 0 0 0 MB0
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//x01 0 0 0 MB1 0 0 0 MB1
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//x10 0 0 0 MB2 0 0 0 MB2
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//x11 0 0 0 MB3 0 0 0 MB3
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//Short Mode:
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//ADDR[2:0] B7 B6 B5 B4 B3 B2 B1 B0
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//x00 0 0 MB1 MB0 0 0 MB1 MB0
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//x10 0 0 MB3 MB2 0 0 MB3 MB2
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//Word Mode:
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//ADDR[2:0] B7 B6 B5 B4 B3 B2 B1 B0
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//x00 MB3 MB2 MB1 MB0 MB3 MB2 MB1 MB0
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//Double Mode:
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//ADDR[2:0] B7 B6 B5 B4 B3 B2 B1 B0
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//000 MB7 MB6 MB5 MB4 MB3 MB2 MB1 MB0
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//so..
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//B0=MB0|MB1|MB2|MB3
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//B1=MB1|MB3|0
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//B2=MB2|0
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//B3=MB3|0
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/*Aligns word on read
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*/
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module emesh_rdalign (/*AUTOARG*/
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// Outputs
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data_out,
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// Inputs
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addr, datamode, data_in
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);
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//Inputs
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input [2:0] addr;
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input [1:0] datamode;
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input [63:0] data_in;
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//Outputs
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output [63:0] data_out;
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//wires
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wire [3:0] byte0_sel;
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wire [31:0] data_mux;
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wire [31:0] data_aligned;
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wire byte1_sel1;
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wire byte1_sel0;
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wire byte2_en;
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wire byte3_en;
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//Shift down high word
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assign data_mux[31:0] = addr[2] ? data_in[63:32] :
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data_in[31:0];
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//Byte0
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assign byte0_sel[3] = addr[1:0]==2'b11;
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assign byte0_sel[2] = addr[1:0]==2'b10;
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assign byte0_sel[1] = addr[1:0]==2'b01;
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assign byte0_sel[0] = addr[1:0]==2'b00;
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//Byte1
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assign byte1_sel1 = datamode[1:0]==2'b01 & addr[1:0]==2'b10;
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assign byte1_sel0 = (datamode[1:0]==2'b01 & addr[1:0]==2'b00) |
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datamode[1:0]==2'b10 |
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datamode[1:0]==2'b11;
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//Byte2
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assign byte2_en = datamode[1:0]==2'b10 |
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datamode[1:0]==2'b11;
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//Byte3
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assign byte3_en = datamode[1:0]==2'b10 |
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datamode[1:0]==2'b11;
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//B0: 32 NANDs,8 NORS
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assign data_aligned[7:0] = {(8){byte0_sel[3]}} & data_mux[31:24] |
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{(8){byte0_sel[2]}} & data_mux[23:16] |
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{(8){byte0_sel[1]}} & data_mux[15:8] |
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{(8){byte0_sel[0]}} & data_mux[7:0];
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//B1:
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assign data_aligned[15:8] = {(8){byte1_sel1}} & data_mux[31:24] |
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{(8){byte1_sel0}} & data_mux[15:8];
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//B2: 8 NANDS
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assign data_aligned[23:16] = {(8){byte2_en}} & data_mux[23:16];
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//B3:
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assign data_aligned[31:24] = {(8){byte3_en}} & data_mux[31:24];
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//lower 32 bits
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assign data_out[31:0] = data_aligned[31:0];
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//Upper 32 bits are pass through
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assign data_out[63:32] = data_in[63:32];
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endmodule // memory_rdalign
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