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289024fd89
- Creating an arbitrary 'src' directory really doesn't help much... - Goal is to make each folder self contained - Make meta repos and individual repos have the same directory structure
62 lines
2.1 KiB
Verilog
62 lines
2.1 KiB
Verilog
/* Aligns data before writing.
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* Incoming data is aligned to lsb's
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*/
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module emesh_wralign (/*AUTOARG*/
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// Outputs
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data_out,
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// Inputs
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datamode, data_in
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);
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input [1:0] datamode;
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input [63:0] data_in;
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output [63:0] data_out;
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wire [3:0] data_size;
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assign data_size[0]= (datamode[1:0]==2'b00);//byte
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assign data_size[1]= (datamode[1:0]==2'b01);//short
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assign data_size[2]= (datamode[1:0]==2'b10);//word
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assign data_size[3]= (datamode[1:0]==2'b11);//double
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//B0(0)
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assign data_out[7:0] = data_in[7:0];
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//B1(16 NAND2S,8 NOR2S)
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assign data_out[15:8] = {(8){data_size[0]}} & data_in[7:0] |
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{(8){(|data_size[3:1])}} & data_in[15:8] ;
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//B2(16 NAND2S,8 NOR2S)
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assign data_out[23:16] = {(8){(|data_size[1:0])}} & data_in[7:0] |
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{(8){(|data_size[3:2])}} & data_in[23:16] ;
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//B3(24 NAND2S,8 NOR3S)
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assign data_out[31:24] = {(8){data_size[0]}} & data_in[7:0] |
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{(8){data_size[1]}} & data_in[15:8] |
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{(8){(|data_size[3:2])}} & data_in[31:24] ;
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//B4(24 NAND2S,8 NOR3S)
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assign data_out[39:32] = {(8){(|data_size[2:0])}} & data_in[7:0] |
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{(8){data_size[3]}} & data_in[39:32] ;
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//B5(24 NAND2S,8 NOR3S)
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assign data_out[47:40] = {(8){data_size[0]}} & data_in[7:0] |
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{(8){(|data_size[2:1])}} & data_in[15:8] |
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{(8){data_size[3]}} & data_in[47:40] ;
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//B6(24 NAND2S,8 NOR3S)
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assign data_out[55:48] = {(8){(|data_size[1:0])}} & data_in[7:0] |
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{(8){data_size[2]}} & data_in[23:16] |
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{(8){data_size[3]}} & data_in[55:48] ;
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//B7(32 NAND2S,16 NOR2S)
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assign data_out[63:56] = {(8){data_size[0]}} & data_in[7:0] |
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{(8){data_size[1]}} & data_in[15:8] |
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{(8){data_size[2]}} & data_in[31:24] |
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{(8){data_size[3]}} & data_in[63:56] ;
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endmodule // memory_wralign
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