mirror of
https://github.com/aolofsson/oh.git
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289024fd89
- Creating an arbitrary 'src' directory really doesn't help much... - Goal is to make each folder self contained - Make meta repos and individual repos have the same directory structure
172 lines
7.0 KiB
Verilog
172 lines
7.0 KiB
Verilog
//#############################################################################
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//# Purpose: Parallella GPIO top #
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//#############################################################################
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//# Author: Ola Jeppsson #
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//# SPDX-License-Identifier: MIT #
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//#############################################################################
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module parallella_gpio(/*AUTOARG*/
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// Outputs
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s_axi_wready, s_axi_rvalid, s_axi_rresp, s_axi_rlast, s_axi_rid,
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s_axi_rdata, s_axi_bvalid, s_axi_bresp, s_axi_bid, s_axi_awready,
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s_axi_arready, gpio_irq,
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// Inouts
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gpio_n, gpio_p,
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// Inputs
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s_axi_wvalid, s_axi_wstrb, s_axi_wlast, s_axi_wid, s_axi_wdata,
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s_axi_rready, s_axi_bready, s_axi_awvalid, s_axi_awsize,
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s_axi_awqos, s_axi_awprot, s_axi_awlock, s_axi_awlen, s_axi_awid,
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s_axi_awcache, s_axi_awburst, s_axi_awaddr, s_axi_arvalid,
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s_axi_arsize, s_axi_arqos, s_axi_arprot, s_axi_arlock, s_axi_arlen,
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s_axi_arid, s_axi_aresetn, s_axi_arcache, s_axi_arburst,
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s_axi_araddr, constant_zero, constant_one, sys_nreset, sys_clk
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);
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//########################################################
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// INTERFACE
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//########################################################
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parameter AW = 32; // address width
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parameter DW = 32;
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parameter PW = 2*AW+40; // packet width
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parameter ID = 12'h7ff; // addr[31:20] id
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parameter S_IDW = 12; // ID width for S_AXI
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parameter NGPIO = 24; // number of gpio pins
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// constants
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input constant_zero; // Always 0
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input constant_one; // Always 1
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//clk, reset
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input sys_nreset; // active low async reset
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input sys_clk; // system clock for AXI
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inout [NGPIO-1:0] gpio_n; // physical gpio pins
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inout [NGPIO-1:0] gpio_p; // physical gpio pins
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wire [NGPIO-1:0] gpio_in; // oh gpio in
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wire [NGPIO-1:0] gpio_out; // oh gpio out
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wire [NGPIO-1:0] gpio_dir; // oh gpio direction
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wire [NGPIO-1:0] pgpio_in; // parallella gpio in
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wire [NGPIO-1:0] pgpio_out; // parallella gpio out
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/*AUTOINPUT*/
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// Beginning of automatic inputs (from unused autoinst inputs)
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input [31:0] s_axi_araddr; // To axi_gpio of axi_gpio.v
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input [1:0] s_axi_arburst; // To axi_gpio of axi_gpio.v
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input [3:0] s_axi_arcache; // To axi_gpio of axi_gpio.v
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input s_axi_aresetn; // To axi_gpio of axi_gpio.v
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input [S_IDW-1:0] s_axi_arid; // To axi_gpio of axi_gpio.v
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input [7:0] s_axi_arlen; // To axi_gpio of axi_gpio.v
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input s_axi_arlock; // To axi_gpio of axi_gpio.v
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input [2:0] s_axi_arprot; // To axi_gpio of axi_gpio.v
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input [3:0] s_axi_arqos; // To axi_gpio of axi_gpio.v
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input [2:0] s_axi_arsize; // To axi_gpio of axi_gpio.v
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input s_axi_arvalid; // To axi_gpio of axi_gpio.v
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input [31:0] s_axi_awaddr; // To axi_gpio of axi_gpio.v
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input [1:0] s_axi_awburst; // To axi_gpio of axi_gpio.v
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input [3:0] s_axi_awcache; // To axi_gpio of axi_gpio.v
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input [S_IDW-1:0] s_axi_awid; // To axi_gpio of axi_gpio.v
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input [7:0] s_axi_awlen; // To axi_gpio of axi_gpio.v
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input s_axi_awlock; // To axi_gpio of axi_gpio.v
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input [2:0] s_axi_awprot; // To axi_gpio of axi_gpio.v
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input [3:0] s_axi_awqos; // To axi_gpio of axi_gpio.v
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input [2:0] s_axi_awsize; // To axi_gpio of axi_gpio.v
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input s_axi_awvalid; // To axi_gpio of axi_gpio.v
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input s_axi_bready; // To axi_gpio of axi_gpio.v
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input s_axi_rready; // To axi_gpio of axi_gpio.v
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input [31:0] s_axi_wdata; // To axi_gpio of axi_gpio.v
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input [S_IDW-1:0] s_axi_wid; // To axi_gpio of axi_gpio.v
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input s_axi_wlast; // To axi_gpio of axi_gpio.v
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input [3:0] s_axi_wstrb; // To axi_gpio of axi_gpio.v
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input s_axi_wvalid; // To axi_gpio of axi_gpio.v
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// End of automatics
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/*AUTOOUTPUT*/
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// Beginning of automatic outputs (from unused autoinst outputs)
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output gpio_irq; // From axi_gpio of axi_gpio.v
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output s_axi_arready; // From axi_gpio of axi_gpio.v
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output s_axi_awready; // From axi_gpio of axi_gpio.v
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output [S_IDW-1:0] s_axi_bid; // From axi_gpio of axi_gpio.v
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output [1:0] s_axi_bresp; // From axi_gpio of axi_gpio.v
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output s_axi_bvalid; // From axi_gpio of axi_gpio.v
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output [31:0] s_axi_rdata; // From axi_gpio of axi_gpio.v
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output [S_IDW-1:0] s_axi_rid; // From axi_gpio of axi_gpio.v
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output s_axi_rlast; // From axi_gpio of axi_gpio.v
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output [1:0] s_axi_rresp; // From axi_gpio of axi_gpio.v
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output s_axi_rvalid; // From axi_gpio of axi_gpio.v
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output s_axi_wready; // From axi_gpio of axi_gpio.v
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// End of automatics
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/*AUTOWIRE*/
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/*AUTOREG*/
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assign constant_zero = 1'b0;
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assign constant_one = 1'b1;
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pgpio #(.NGPIO(NGPIO),.NPS(NGPIO))
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pgpio (.ps_gpio_i (gpio_in[NGPIO-1:0]),
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.ps_gpio_o (gpio_out[NGPIO-1:0]),
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.ps_gpio_t (~gpio_dir[NGPIO-1:0]),
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/*AUTOINST*/
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// Inouts
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.gpio_p (gpio_p[NGPIO-1:0]),
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.gpio_n (gpio_n[NGPIO-1:0]));
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axi_gpio #(.S_IDW(S_IDW),.AW(AW),.N(NGPIO),.ID(ID))
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axi_gpio (
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.gpio_out (gpio_out[NGPIO-1:0]),
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.gpio_dir (gpio_dir[NGPIO-1:0]),
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.gpio_in (gpio_in[NGPIO-1:0]),
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/*AUTOINST*/
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// Outputs
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.gpio_irq (gpio_irq),
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.s_axi_arready (s_axi_arready),
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.s_axi_awready (s_axi_awready),
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.s_axi_bid (s_axi_bid[S_IDW-1:0]),
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.s_axi_bresp (s_axi_bresp[1:0]),
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.s_axi_bvalid (s_axi_bvalid),
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.s_axi_rdata (s_axi_rdata[31:0]),
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.s_axi_rid (s_axi_rid[S_IDW-1:0]),
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.s_axi_rlast (s_axi_rlast),
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.s_axi_rresp (s_axi_rresp[1:0]),
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.s_axi_rvalid (s_axi_rvalid),
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.s_axi_wready (s_axi_wready),
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// Inputs
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.sys_nreset (sys_nreset),
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.sys_clk (sys_clk),
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.s_axi_araddr (s_axi_araddr[31:0]),
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.s_axi_arburst (s_axi_arburst[1:0]),
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.s_axi_arcache (s_axi_arcache[3:0]),
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.s_axi_aresetn (s_axi_aresetn),
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.s_axi_arid (s_axi_arid[S_IDW-1:0]),
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.s_axi_arlen (s_axi_arlen[7:0]),
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.s_axi_arlock (s_axi_arlock),
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.s_axi_arprot (s_axi_arprot[2:0]),
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.s_axi_arqos (s_axi_arqos[3:0]),
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.s_axi_arsize (s_axi_arsize[2:0]),
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.s_axi_arvalid (s_axi_arvalid),
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.s_axi_awaddr (s_axi_awaddr[31:0]),
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.s_axi_awburst (s_axi_awburst[1:0]),
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.s_axi_awcache (s_axi_awcache[3:0]),
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.s_axi_awid (s_axi_awid[S_IDW-1:0]),
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.s_axi_awlen (s_axi_awlen[7:0]),
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.s_axi_awlock (s_axi_awlock),
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.s_axi_awprot (s_axi_awprot[2:0]),
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.s_axi_awqos (s_axi_awqos[3:0]),
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.s_axi_awsize (s_axi_awsize[2:0]),
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.s_axi_awvalid (s_axi_awvalid),
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.s_axi_bready (s_axi_bready),
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.s_axi_rready (s_axi_rready),
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.s_axi_wdata (s_axi_wdata[31:0]),
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.s_axi_wid (s_axi_wid[S_IDW-1:0]),
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.s_axi_wlast (s_axi_wlast),
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.s_axi_wstrb (s_axi_wstrb[3:0]),
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.s_axi_wvalid (s_axi_wvalid));
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endmodule // parallella_gpio
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// Local Variables:
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// verilog-library-directories:("." "../../axi/hdl" "../../common/hdl" "../../emesh/hdl" "../../parallella/hdl")
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// End:
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