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289024fd89
- Creating an arbitrary 'src' directory really doesn't help much... - Goal is to make each folder self contained - Make meta repos and individual repos have the same directory structure
108 lines
2.8 KiB
Verilog
108 lines
2.8 KiB
Verilog
module mrx_protocol (/*AUTOARG*/
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// Outputs
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fifo_access, fifo_packet,
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// Inputs
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rx_clk, nreset, datasize, lsbfirst, io_access, io_packet
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);
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//#####################################################################
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//# INTERFACE
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//#####################################################################
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//parameters
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parameter PW = 104; // packet width (core)
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parameter NMIO = 8; // io packet width
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parameter CW = $clog2(2*PW/NMIO); // transfer count width
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//clock and reset
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input rx_clk; // rx clock
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input nreset; // async active low reset
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//config
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input [7:0] datasize; // dynamic width of output data
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input lsbfirst;
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//16 bit interface
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input io_access; // access signal from IO
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input [2*NMIO-1:0] io_packet; // data from IO
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//wide input interface
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output fifo_access; // access for fifo
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output [PW-1:0] fifo_packet; // packet for fifo
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//#####################################################################
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//# BODY
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//#####################################################################
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//regs
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reg [2:0] mrx_state;
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reg [CW-1:0] mrx_count;
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reg fifo_access;
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wire shift;
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wire transfer_done;
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//##########################
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//# STATE MACHINE
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//##########################
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`define MRX_IDLE 3'b000
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`define MRX_BUSY 3'b001
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always @ (posedge rx_clk or negedge nreset)
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if(!nreset)
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mrx_state[2:0] <= `MRX_IDLE;
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else
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case (mrx_state[2:0])
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`MRX_IDLE: mrx_state[2:0] <= io_access ? `MRX_BUSY : `MRX_IDLE;
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`MRX_BUSY: mrx_state[2:0] <= ~io_access ? `MRX_IDLE : `MRX_BUSY;
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default: mrx_state[2:0] <= 'b0;
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endcase // case (mrx_state[2:0])
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//tx word counter
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always @ (posedge rx_clk)
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if((mrx_state[2:0]==`MRX_IDLE) | transfer_done)
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mrx_count[CW-1:0] <= datasize[CW-1:0];
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else if(mrx_state[2:0]==`MRX_BUSY)
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mrx_count[CW-1:0] <= mrx_count[CW-1:0] - 1'b1;
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assign transfer_done = (mrx_count[CW-1:0]==1'b1) & (mrx_state[2:0]==`MRX_BUSY);
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assign shift = (mrx_state[2:0]==`MRX_BUSY);
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//pipeline access signal
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always @ (posedge rx_clk or negedge nreset)
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if(!nreset)
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fifo_access <= 'b0;
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else
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fifo_access <= transfer_done;
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//##########################
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//# SHIFT REGISTER
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//##########################
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oh_ser2par #(.PW(PW),
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.SW(2*NMIO))
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ser2par (// Outputs
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.dout (fifo_packet[PW-1:0]),
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// Inputs
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.clk (rx_clk),
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.din (io_packet[2*NMIO-1:0]),
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.lsbfirst (lsbfirst),
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.shift (shift)
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);
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endmodule // mrx_protocol
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// Local Variables:
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// verilog-library-directories:("." "../../common/hdl")
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// End:
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