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161 lines
5.2 KiB
Markdown
161 lines
5.2 KiB
Markdown
SPI: Serial Peripheral Interface
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=======================================
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1. [Features](#features)
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2. [Examples](#examples)
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3. [Master Registers](#master-registers)
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4. [Slave Registers](#slave-registers)
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5. [Interface](#interface)
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6. [Code](#code)
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7. [Driver](#driver)
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8. [License](#license)
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9. [Authors](#authors)
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## Features
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* Standalone general purpose SPI master
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* Standalone general purpose SPI slave
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* Available as configurable master/slave module
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* Support for epiphany mesh transactions
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* Support for 64 bit data and address
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## Examples
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**SPI_WRITE:**
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```
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DEADBEEF_00000020_00000008_01_0000 // write command + slave address
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DEADBEEF_00000042_00000008_01_0100 // byte to write (42)
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```
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**SPI_READ:**
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```
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DEADBEEF_000000A0_00000008_01_0000 // read command + slave address
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00000000_00000000_00000008_01_0100 // (dummy byte to generate sclk)
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```
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**REMOTE SPI WRITE:**
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```
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DEADBEEF_00000000_00000008_01_0000 // write command + slave config address
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DEADBEEF_00000010_00000008_01_0200 // lsb-first config
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DEADBEEF_00000010_00000000_03_0200 // configure master as lsbfirst
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DEADBEEF_000007C1_00000008_03_0000 // remote write command + 1st emesh byte
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00000000_82800000_00000008_05_0000 // 32b destination address
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fedcba98_76543210_00000008_07_0400 // 64b data payload
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```
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## Master Registers
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| Register Name |Addr[7:0]| Access | Default | Description |
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|---------------|---------|--------|---------|-------------------------------|
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| SPI_CONFIG | 0x0 | RD/WR | L | Configuration register |
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| SPI_STATUS | 0x1 | RD/WR | n/a | Status register |
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| SPI_CLKDIV | 0x2 | RD/WR | H | Baud rate setting |
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| SPI_TX | 0x8 | WR | n/a | Transmit FIFO |
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| SPI_RX | 0x10 | RD | n/a | Receiver data register |
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**SPI_CONFIG:**
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| FIELD | DESCRIPTION |
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|-------- |-------------------------------------|
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| [0] | Disable spi controller |
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| [1] | Enable output interrupt |
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| [2] | cpol |
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| [3] | cpha |
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| [4] | LSB first transfer mode |
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| [5] | SS control mode (1=manual mode) |
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| [6] | Controls SS pin in manual SS mode |
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**SPI_STATUS:**
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| FIELD | DESCRIPTION |
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|-------- |-------------------------------------|
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| [0] | 1: Split transaction data is ready |
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| [1] | 1: SPI transfer active |
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| [2] | 1: TX FIFO at half full |
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**SPI_CLKDIV:**
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| FIELD | DESCRIPTION |
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|-------- |-------------------------------------|
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| [7:0] | Clock divider value |
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| | Ratio=1<<clkdiv[7:0] |
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**SPI_TX:**
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Eight readable byte wide registers.
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**SPI_RX:**
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Eight addressable byte wide registers.
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**SPI_USER:**
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Up to 16 user specified byte wide registers
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## Slave Registers
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| Register Name |Addr[7:0]| Access | Default | Description |
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|---------------|---------|--------|---------|---------------------------------|
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| SPI_CONFIG | 0x0 | RD/WR | L | Configuration register |
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| SPI_STATUS | 0x1 | RD/WR | n/a | Status register |
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| SPI_TX | 0x8 | RD | n/a | Split transaction return data |
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| SPI_USER | 0x20 | RD/WR | n/a | User defined registers |
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**SPI_CONFIG (0x0): **
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| FIELD | DESCRIPTION |
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|-------- |-------------------------------------|
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| [0] | Disable spi |
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| [1] | Enable output interrupt |
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| [2] | cpol |
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| [3] | cpha |
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| [4] | LSB first transfer |
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| [5] | User regs enable |
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**SPI_STATUS (0x1): **
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| FIELD | DESCRIPTION |
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|-------- |-------------------------------------|
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| [0] | 1: Split transaction data is ready |
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**SPI_TX (0x8) :**
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Eight readable byte wide registers.
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**SPI_RX (0x20) :**
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Eight addressable byte wide registers.
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**SPI_USER:**
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Up to 16 user specified byte wide registers
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## Interface
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```
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input nreset; // asynch active low reset
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input clk; // core clock
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output spi_irq; // interrupt output
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input access_in; // access from core
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input [PW-1:0] packet_in; // packet from core
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input wait_in; // pushback from core
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output access_out; // access to core
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output [PW-1:0] packet_out; // packet to core
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output wait_out; // pushback to core
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output m_sclk; // master clock to IO
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output m_mosi; // master output to IO
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output m_ss; // slave select to IO
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input m_miso; // master input from IO
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input s_sclk; // slave clock from IO
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input s_mosi; // slave input from IO
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input s_ss; // slave select from IO
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output s_miso; // slave output to IO
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```
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## Code
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* [spi.v](hdl/spi.v)
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## Driver
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* driver/spi_driver.c
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* driver/spi_driver.h
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## License
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* MIT
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## Authors
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* Andreas Olofsson
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