FPGA/oh

mirror of https://github.com/aolofsson/oh.git synced 2025-01-17 20:02:53 +08:00

History

aolofsson b8a962e61b Fixing random compile issue with -y include in surelog

2022-10-17 21:06:59 -04:00

..

Flattening directory tree (again)

2022-06-21 14:48:48 -04:00

Flattening directory tree (again)

2022-06-21 14:48:48 -04:00

Fixing random compile issue with -y include in surelog

2022-10-17 21:06:59 -04:00

Finishing minimal icarus "standardized" testbench

2022-06-28 23:18:00 -04:00

README.md

Flattening directory tree (again)

2022-06-21 14:48:48 -04:00

stdlib.py

Adding sc place holder

2022-09-29 22:21:04 -04:00

README.md

STDLIB

STDLIB is a library of low level vectoried building blocks for control and datapath logic.
Where appropriate, parameters are included to enable soft and hard-coded implementation.
Some library cells call on others cells within the library