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61 lines
1.7 KiB
Verilog
61 lines
1.7 KiB
Verilog
module dv_top ();
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parameter DW = 64; // Memory width
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parameter MAW = 15; // Memory address width
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//regs/wires
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reg [1023:0] filename;
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wire [DW-1:0] ext_packet;
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire nreset; // From dv_ctrl of dv_ctrl.v
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wire start; // From dv_ctrl of dv_ctrl.v
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wire stim_access; // From stimulus of stimulus.v
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wire stim_done; // From stimulus of stimulus.v
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wire [DW-1:0] stim_packet; // From stimulus of stimulus.v
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wire vdd; // From dv_ctrl of dv_ctrl.v
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wire vss; // From dv_ctrl of dv_ctrl.v
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// End of automatics
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assign test_done = 1'b1;
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assign dut_active = 1'b1;
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//Reset and clocks
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dv_ctrl dv_ctrl(.clk1 (ext_clk),
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.clk2 (dut_clk),
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/*AUTOINST*/
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// Outputs
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.nreset (nreset),
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.start (start),
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.vdd (vdd),
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.vss (vss),
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// Inputs
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.dut_active (dut_active),
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.stim_done (stim_done),
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.test_done (test_done));
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//Stimulus
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assign ext_start = start;
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assign ext_access = 'b0;
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assign ext_packet = 'b0;
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assign dut_wait = 'b0;
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stimulus #(.DW(DW),.MAW(MAW),.HEXFILE("firmware.hex"))
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stimulus(
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/*AUTOINST*/
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// Outputs
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.stim_access (stim_access),
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.stim_packet (stim_packet[DW-1:0]),
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.stim_done (stim_done),
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// Inputs
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.nreset (nreset),
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.ext_start (ext_start),
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.ext_clk (ext_clk),
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.ext_access (ext_access),
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.ext_packet (ext_packet[DW-1:0]),
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.dut_clk (dut_clk),
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.dut_wait (dut_wait));
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endmodule // unmatched end(function|task|module|primitive|interface|package|class|clocking)
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