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36 lines
1.6 KiB
Verilog
36 lines
1.6 KiB
Verilog
//#############################################################################
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//# Function: DUT wrapper template/stub
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//#############################################################################
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//# Author: Andreas Olofsson #
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//# License: MIT (see LICENSE file in OH! repository) #
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//#############################################################################
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module tb_dut
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#(parameter PW = 256, // packet width
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parameter N = 36, // ctrl/status width
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parameter TARGET = "DEFAULT" // physical synthesis/sim target
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)
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(// basic test interface
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input clk, // standard clock used for interface
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input fastclk, // fast clock (optional for core)
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input slowclk, // fast clock (optional for core)
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input nreset, // async active low reset
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input go, // go dut (if not self-booting)
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input [N-1:0] ctrl, // env generic ctrl vector
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// environment packet interface
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input valid, // env packet valid signal
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input [PW-1:0] packet, // env packet to drive
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input ready, // env is ready for packet
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// dut status signals
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output dut_active, // dut reset sequence done
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output dut_error, // per cycle error signal
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output dut_done, // dut is done
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output [N-1:0] dut_status, // dut generic status vector
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// dut response packets
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output dut_valid, //dut packet valid signal
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output [PW-1:0] dut_packet, // dut packet to drive
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output dut_ready // dut is ready for packet
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);
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endmodule // tb_dut
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