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f7edd3cb37
Copy of z7020 project. Small changes, 99% could be reused. Diff vs. z7020 in: parallella/fpga/headless_e16_z7010-vs-z7020.diff Compiles but NOT TESTED. Signed-off-by: Ola Jeppsson <ola@adapteva.com>
58 lines
2.4 KiB
Diff
58 lines
2.4 KiB
Diff
--- headless_e16_z7010/system_params.tcl 2016-03-11 12:19:17.200943709 +0100
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+++ headless_e16_z7020/system_params.tcl 2015-11-09 19:23:07.699404317 +0100
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@@ -6,7 +6,7 @@
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set projdir ./
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#Device name
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-set partname "xc7z010clg400-1"
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+set partname "xc7z020clg400-1"
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#Paths to all IP blocks to use in Vivado "system.bd"
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@@ -19,4 +19,5 @@
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set constraints_files [list \
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../parallella_timing.xdc \
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../parallella_io.xdc \
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+ ../parallella_7020_io.xdc \
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]
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--- headless_e16_z7010/system_bd.tcl 2016-03-11 15:15:20.061868891 +0100
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+++ headless_e16_z7020/system_bd.tcl 2016-03-11 15:59:44.849627304 +0100
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@@ -29,7 +29,7 @@
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# If you do not already have a project created,
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# you can create a project using the following command:
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-# create_project project_1 myproj -part xc7z010clg400-1
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+# create_project project_1 myproj -part xc7z020clg400-1
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# CHECKING IF PROJECT EXISTS
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if { [get_projects -quiet] eq "" } {
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@@ -148,8 +148,8 @@
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set cclk_n [ create_bd_port -dir O cclk_n ]
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set cclk_p [ create_bd_port -dir O cclk_p ]
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set chip_nreset [ create_bd_port -dir O chip_nreset ]
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- set gpio_n [ create_bd_port -dir IO -from 11 -to 0 gpio_n ]
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- set gpio_p [ create_bd_port -dir IO -from 11 -to 0 gpio_p ]
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+ set gpio_n [ create_bd_port -dir IO -from 23 -to 0 gpio_n ]
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+ set gpio_p [ create_bd_port -dir IO -from 23 -to 0 gpio_p ]
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set hdmi_clk [ create_bd_port -dir O hdmi_clk ]
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set hdmi_d [ create_bd_port -dir O -from 23 -to 8 hdmi_d ]
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set hdmi_de [ create_bd_port -dir O hdmi_de ]
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@@ -186,7 +186,7 @@
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# Create instance: parallella_base_0, and set properties
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set parallella_base_0 [ create_bd_cell -type ip -vlnv www.parallella.org:user:parallella_base:1.0 parallella_base_0 ]
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- set_property -dict [ list CONFIG.NGPIO {12} ] $parallella_base_0
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+ set_property -dict [ list CONFIG.NGPIO {24} ] $parallella_base_0
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# Create instance: proc_sys_reset_0, and set properties
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set proc_sys_reset_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_0 ]
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--- headless_e16_z7010/build.sh 2016-03-11 12:16:03.342803755 +0100
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+++ headless_e16_z7020/build.sh 2016-03-11 15:54:58.503321785 +0100
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@@ -2,5 +2,5 @@
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rm system_wrapper.bit.bin bit2bin.bin
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vivado -mode batch -source run.tcl
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bootgen -image bit2bin.bif -split bin
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-cp system_wrapper.bit.bin parallella_e16_headless_gpiose_7010.bit.bin
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+cp system_wrapper.bit.bin parallella_e16_headless_gpiose_7020.bit.bin
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#archive results based on time stamp
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