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f7edd3cb37
Copy of z7020 project. Small changes, 99% could be reused. Diff vs. z7020 in: parallella/fpga/headless_e16_z7010-vs-z7020.diff Compiles but NOT TESTED. Signed-off-by: Ola Jeppsson <ola@adapteva.com>
23 lines
408 B
Tcl
23 lines
408 B
Tcl
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#Design name ("system" recommended)
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set design system
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#Project directory ("." recommended)
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set projdir ./
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#Device name
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set partname "xc7z010clg400-1"
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#Paths to all IP blocks to use in Vivado "system.bd"
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set ip_repos [list "../parallella_base"]
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#All source files
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set hdl_files []
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#All constraints files
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set constraints_files [list \
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../parallella_timing.xdc \
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../parallella_io.xdc \
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]
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