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Modify build script to output: parallella_e16_headless_gpiose_7020.bit.bin This is the same naming convention used by the old elink code. Signed-off-by: Ola Jeppsson <ola@adapteva.com>
13 lines
306 B
Tcl
13 lines
306 B
Tcl
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#STEP1: DEFINE KEY PARAMETERS
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source ./system_params.tcl
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#STEP2: CREATE PROJECT AND READ IN FILES
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source ../../../common/fpga/system_init.tcl
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#STEP 3 (OPTIONAL): EDIT system.bd in VIVADO gui, then go to STEP 4.
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##...
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#STEP 4: SYNTEHSIZE AND CREATE BITSTRAM
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source ../../../common/fpga/system_build.tcl
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