1
0
mirror of https://github.com/aolofsson/oh.git synced 2025-01-17 20:02:53 +08:00
oh/xilibs/hdl/BUFG.v
Andreas Olofsson ebaac22700 Cleanup
2015-04-21 21:43:16 -04:00

13 lines
136 B
Verilog

module BUFG (/*AUTOARG*/
// Outputs
O,
// Inputs
I
);
input I;
output O;
assign O = I;
endmodule // IBUFDS