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87 lines
3.9 KiB
Verilog
87 lines
3.9 KiB
Verilog
//#############################################################################
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//# Purpose: Simple clock divider (modulo 2) #
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//# clkdiv: 0-->divide by 1 #
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//# clkdiv: 1-->divide by 2 #
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//# clkdiv: 2-->divide by 4 #
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//# clkdiv: 2-->divide by 8 etc.. #
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//#############################################################################
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//# Author: Andreas Olofsson #
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//# License: MIT (see below) #
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//#############################################################################
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module oh_clockdiv(/*AUTOARG*/
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// Outputs
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period_match, phase_match, clkout,
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// Inputs
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clk, nreset, en, clkdiv
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);
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parameter DW = 8; // divider counter width
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parameter CW = $clog2(DW); // config width
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input clk; // main clock
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input nreset; // async active low reset
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input en; // counter enable
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input [CW-1:0] clkdiv; // counter width
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output period_match; // period match
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output phase_match; // phase match
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output clkout; // output clock
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reg [DW-1:0] counter; //free running counter!
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reg clkout;
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//baud counter
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always @ (posedge clk or negedge nreset)
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if(!nreset)
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counter[7:0] <= 'b0;
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else if(en)
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if(period_match)
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counter[7:0] <= 'b0;
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else
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counter[7:0] <= counter[7:0] + 1'b1;
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assign period_match=(counter[DW-1:0]==((1<<clkdiv[CW-1:0])-1'b1));
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assign phase_match =(counter[DW-1:0]==((1<<(clkdiv[CW-1:0])>> 1)-1'b1));
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//clock generator
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always @ (posedge clk or negedge nreset)
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if(!nreset)
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clkout <= 1'b0;
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else if(phase_match)
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clkout <= 1'b1;
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else if(period_match)
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clkout <= 1'b0;
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endmodule // oh_clockdiv
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///////////////////////////////////////////////////////////////////////////////
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// The MIT License (MIT) //
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// //
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// Copyright (c) 2015-2016, Adapteva, Inc. //
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// //
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// Permission is hereby granted, free of charge, to any person obtaining a //
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// copy of this software and associated documentation files (the "Software") //
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// to deal in the Software without restriction, including without limitation //
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// the rights to use, copy, modify, merge, publish, distribute, sublicense, //
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// and/or sell copies of the Software, and to permit persons to whom the //
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// Software is furnished to do so, subject to the following conditions: //
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// //
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// The above copyright notice and this permission notice shall be included //
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// in all copies or substantial portions of the Software. //
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// //
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS //
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// OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF //
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// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. //
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// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY //
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// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT //
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// OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR //
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// THE USE OR OTHER DEALINGS IN THE SOFTWARE. //
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// //
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///////////////////////////////////////////////////////////////////////////////
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