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54 lines
1.3 KiB
Verilog
54 lines
1.3 KiB
Verilog
//##################################################################
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//# ***DUAL DATA RATE INPUT***
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//#
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//# * Equivalent to "SAME_EDGE_PIPELINED" for xilinx
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//# * din sampled on rising edge of clk
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//# * din sampled on falling edge of clk
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//# * q1 holds rising edge data
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//# * q2 holds falling edge data
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//#
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//##################################################################
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module oh_iddr (/*AUTOARG*/
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// Outputs
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q1, q2,
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// Inputs
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clk, ce, din
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);
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//parameters
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parameter DW = 32; // width of interface
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//interface
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input clk; // clock
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input ce; // clock enable, set to high to clock in data
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input [DW-1:0] din; // data input
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output [DW-1:0] q1; // iddr rising edge sampled data
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output [DW-1:0] q2; // iddr falling edge sampled data
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//regs("sl"=stable low, "sh"=stable high)
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reg [DW-1:0] q1_sl;
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reg [DW-1:0] q2_sh;
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reg [DW-1:0] q1;
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reg [DW-1:0] q2;
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// rising edge sample
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always @ (posedge clk)
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if(ce)
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q1_sl[DW-1:0] <= din[DW-1:0];
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// falling edge sample
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always @ (negedge clk)
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q2_sh[DW-1:0] <= din[DW-1:0];
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// pipeline for alignment
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always @ (posedge clk)
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begin
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q1[DW-1:0] <= q1_sl[DW-1:0];
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q2[DW-1:0] <= q2_sh[DW-1:0];
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end
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endmodule // oh_iddr
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