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Andreas Olofsson 0214df5804 Complete redesign of erx io logic

-Building from primitives
-Work in progress, not quite complete

2015-05-13 23:26:41 -04:00

common

Cleaning up clock divider

2015-05-06 12:26:07 -04:00

edma

Making dma quiet until implemented

2015-05-03 23:23:02 -04:00

elink

Complete redesign of erx io logic

2015-05-13 23:26:41 -04:00

emailbox

Making FIFO/memories easier to use

2015-05-07 23:50:34 -04:00

emesh/hdl

Fixing syntax errors caught in synthesis

2015-05-06 12:27:13 -04:00

emmu

Separating rd/wr wait for pipeline stall

2015-05-04 17:09:23 -04:00

memory

Making FIFO/memories easier to use

2015-05-07 23:50:34 -04:00

xilibs

Cleanup

2015-05-07 23:49:50 -04:00

.gitignore

Adding register access from RX

2015-04-27 23:51:00 -04:00

CONTRIBUTING.md

Basic infrastructure

2015-04-21 21:36:37 -04:00

COPYING

Basic infrastructure

2015-04-21 21:36:37 -04:00

LICENSE

Initial commit

2015-04-21 21:16:42 -04:00

README.md

Massive commit sequence coming...

2015-04-23 17:48:12 -04:00

README.md

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OH!

Open Hardware (Pure and Simple)

(work in progress...)

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