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c91c7abbbc
Testbench is split between the synthesizable transactors and non-synthesizable parts to allow reuse of transactors in the newly added verilator test bench
40 lines
600 B
Verilog
40 lines
600 B
Verilog
module dv_emmu_tb;
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reg clk;
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reg reset;
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reg go;
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//Clock
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always
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#10 clk = ~clk;
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initial
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begin
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$display($time, " << Starting the Simulation >>");
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#0
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clk = 1'b0; // at time 0
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reset = 1'b1; // reset is active
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#100
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reset = 1'b0; // at time 100 release reset
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#100
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go = 1'b1;
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#10000
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$finish;
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end
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//Waveform dump
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initial
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begin
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$dumpfile("test.vcd");
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$dumpvars(0, dv_emmu);
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end
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dv_emmu dv_emmu
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(.clk (clk),
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.reset (reset),
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.go (go));
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endmodule
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