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041f477363
-The current testbench has a big pause between frames, whereas the chip might push out back to back frames with only a single cycle pause between frames. It seems possible that the old logic would have been a problem, since there two incorrect states that took 2 cycles to settle. This would not have been a problem with bursting or frames with many nops between. Let's see.... -The correct way to verify this is to 1.) Improve TX to make performance as good as on the chip (less stalls) 2.) Create a testbench witht the chip reference code. -In the meantime, we compile and pray...
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OH!
An Open Hardware Library for Chip and FPGA designers written in Verilog
CONTENT
| Spec | Description |
|---|---|
| common | Common utility HW modules and scripts |
| edma | DMA module |
| emesh | Epiphany emesh related circuits |
| elink | Epiphany point to point LVDS link |
| emailbox | Simple mailbox with interrupt output |
| emmu | Simple memory transaction translation unit |
| etrace | Simple logic analyzer |
| memory | Various simple memory structures (RAM/FIFO) |
| xilibs | Simulation modules for Xilinx primitives |
LICENSE
The OH! repository source code is licensed under the MIT license unless otherwise specified. See LICENSE for MIT copyright terms. Design specific licenses can be found in the folder root (eg: aes/LICENSE)
CONTRIBUTING
Instructions for contributing can be found HERE.