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206 lines
7.8 KiB
Verilog
206 lines
7.8 KiB
Verilog
/*******************************************************************************
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* Function: Memory Mapped Transaction --> Packet Converter
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* Author: Andreas Olofsson
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* License: MIT (see LICENSE file in OH! repository)
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*
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* Documentation:
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*
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* The following table shows the field mapping for different AW's:
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*
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* | Packet | AW16 | AW32 | AW64 | AW128 |
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* |---------|---------|----------|--------|---------|
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* | 15:0 | DA,CMD | CMD | CMD | CMD |
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* | 47:16 | D/SA,DA | DA0 | DA0 | DA0 |
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* | 79:48 | **** | D0/SA0 | D0/SA0 | D0/SA0 |
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* | 111:80 | **** | D1/0 | D1/SA1 | D1/SA1 |
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* |---------|---------|----------|--------|---------|
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* | 143:112 | **** | *** | DA1 | DA1 |
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* |---------|---------|----------|--------|---------|
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* | 167:144 | **** | *** | D2 | D2/SA2 |
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* | 207:176 | *** | **** | D3 | D3/SA3 |
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* | 239:208 | **** | **** | **** | DA2 |
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* | 271:240 | **** | **** | **** | DA3 |
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* |---------|---------|----------|--------|---------|
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* | 303:272 | **** | **** | *** | D4 |
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* | 335:304 | **** | **** | **** | D5 |
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* | 367:336 | **** | **** | **** | D6 |
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* | 399:368 | **** | **** | **** | D7 |
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*
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* The following list shows the widths supported for each AW
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*
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* |Packet | AW16 | AW32 | AW64 | AW128 |
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* |---------------|-------|--------|--------|--------|
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* |minimum | 40 | 72+8 | 136+8 | 264+8 |
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* |double/atomics | -- | 104+8 | 200+8 | 392+8 |
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*
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* The command field has the following options:
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*
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*
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* | Command[15:0] | 15:12 | 11:8 | 7 | 6:4 | 3:0 |
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* |-----------------|---------|---------|-----------|-------|-------|
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* | WRITE-SINGLE | | | LOCAL | SIZE[2:0] | 0000 |
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* | WRITE-IRQ | | | LOCAL | SIZE[2:0] | 0001 |
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* | WRITE-BURST | | LEN[3:0]| LOCAL | SIZE[2:0] | 0010 |
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* | WRITE-BURSTDATA | | | STOP | | 0011 |
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* | WRITE-MULTICAST | | | LOCAL | SIZE[2:0] | 0100 |
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* | WRITE-IO | | | LOCAL | 0,DIR[1:0]| 0101 |
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* | TBD | | | LOCAL | SIZE[2:0] | 0110 |
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* | TBD | | | LOCAL | SIZE[2:0] | 0111 |
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* |-----------------|------- |---------|-------|-----------|-------|
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* | READ | | LEN[3:0]| LOCAL | SIZE[2:0] | 1000 |
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* | ATOMIC-ADD | | | LOCAL | SIZE[2:0] | 1001 |
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* | ATOMIC-AND | | | LOCAL | SIZE[2:0] | 1010 |
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* | ATOMIC-OR | | | LOCAL | SIZE[2:0] | 1011 |
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* | ATOMIC-XOR | | | LOCAL | SIZE[2:0] | 1100 |
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* | CAS | | | LOCAL | SIZE[2:0] | 1101 |
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* | READ-IO | | | LOCAL | 0,DIR[1:0]| 1110 |
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* | TBD | | | LOCAL | 0,DIR[1:0]| 1111 |
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*
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* SIZE DECODE:
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* 000=8b
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* 001=16b
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* 010=32b
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* 011=64b
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* 100=128b
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* 1xx=reserved
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*
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* DIR DECODE:
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* 00=north
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* 01=east
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* 10=west
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* 11=south
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*
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* Basic commands at bits [7:0] for all address widths
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* AW32/AW64/AW128 formats are compatible
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* AW16 format is a standalone format not compatible with any other
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* CMD[3] indicates
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* Near/Far indicates whether to enable AW or AW/2 packet width
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* All transactions are LSB aligned
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* No return address for AW16 (point to point)
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*
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******************************************************************************/
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module emesh2packet
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#(parameter AW = 64,
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parameter PW = 144)
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(
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//Emesh signal bundle
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input [3:0] opcode_in,
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input [2:0] size_in,//size of each transfer
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input [3:0] burst_in,//length of burst (up to 16)
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input [7:0] ctrl_in,
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input local_in,//local address
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input stop_in,
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input [15:0] cmd_out,//transaction command
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input [AW-1:0] dstaddr_in, //destination address
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input [AW-1:0] srcaddr_in, //source address (for reads)
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input [2*AW-1:0] data_in, //data
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//Output packet
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output [PW-1:0] packet_out
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);
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//############################################
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// Hard Coded selector for read/write formats
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//############################################
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assign cmd_out[3:0] = opcode_in[3:0];
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assign cmd_out[6:4] = size_in[2:0];
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assign cmd_out[7] = local_in
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assign cmd_out[15:8] = ctrl_in[7:0];
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assign write = ~cmd_out[3];
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generate
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//############################
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// 16-Bit ("lite/apb like")
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//############################
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if(AW==16) begin : aw16
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if(PW==40) begin : p40
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assign packet_out[7:0] = cmd_out[7:0];
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assign packet_out[23:8] = dstaddr_out[15:0];
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assign packet_out[39:24] = write ? data_out[15:0]:
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srcaddr_out[15:0];
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end
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else begin: perror
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initial
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$display ("Combo not supported (PW=%ds AW==%ds)", PW,AW);
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end
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end // block: aw16
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//######################
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// 32-Bit
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//######################
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if(AW==32) begin : aw32
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if(PW==80) begin: p80
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assign packet_out[15:0] = cmd_out[15:0];
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assign packet_out[47:16] = dstaddr_out[31:0];
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assign packet_out[79:48] = write ? data_out[31:0] :
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srcaddr_out[31:0];
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end
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else if(PW==112) begin: p112
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assign packet_out[15:0] = cmd_out[15:0];
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assign packet_out[47:16] = dstaddr_out[31:0];
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assign packet_out[79:48] = write ? data_out[31:0] :
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srcaddr_out[31:0];
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assign packet_out[111:80] = data_out[63:32];
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end
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else begin: perror
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initial
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$display ("Combo not supported (PW=%ds AW==%ds)", PW,AW);
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end
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end // block: aw32
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//######################
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// 64-Bit
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//######################
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if(AW==64) begin : aw64
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if(PW==144) begin: p144
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assign packet_out[15:0] = cmd_out[15:0];
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assign packet_out[47:16] = dstaddr_out[31:0];
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assign packet_out[111:48] = write ? data_out[63:0] :
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srcaddr_out[63:0];
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assign packet_out[143:112] = dstaddr_out[63:32];
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end
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else if(PW==208) begin: p208
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assign packet_out[15:0] = cmd_out[15:0];
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assign packet_out[47:16] = dstaddr_out[31:0];
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assign packet_out[111:48] = write ? data_out[63:0] :
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srcaddr_out[63:0];
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assign packet_out[143:112] = dstaddr_out[63:32];
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assign packet_out[207:144] = data_out[127:64];
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end
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else begin: perror
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initial
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$display ("Combo not supported (PW=%ds AW==%ds)", PW,AW);
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end
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end // block: aw64
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//######################
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// 128-Bit
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//######################
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if(AW==128) begin : aw128
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if(PW==272) begin: p272
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assign packet_out[15:0] = cmd_out[15:0];
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assign packet_out[47:16] = dstaddr_out[31:0];
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assign packet_out[111:48] = write ? data_out[63:0] :
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srcaddr_out[63:0];
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assign packet_out[143:112] = dstaddr_out[63:32];
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assign packet_out[207:144] = write ? data_out[127:64] :
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srcaddr_out[127:64];
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assign packet_out[271:208] = dstaddr_out[127:64];
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end
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else if(PW==400) begin: p400
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assign packet_out[15:0] = cmd_out[15:0];
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assign packet_out[47:16] = dstaddr_out[31:0];
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assign packet_out[111:48] = write ? data_out[63:0] :
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srcaddr_out[63:0];
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assign packet_out[143:112] = dstaddr_out[63:32];
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assign packet_out[207:144] = write ? data_out[127:64] :
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srcaddr_out[127:64];
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assign packet_out[271:208] = dstaddr_out[127:64];
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assign packet_out[399:272] = data_out[255:128];
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end
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else begin: perror
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initial
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$display ("Combo not supported (PW=%ds AW==%ds)", PW,AW);
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end
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end // block: aw128
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endgenerate
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endmodule // emesh2packet
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