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134 lines
3.1 KiB
Verilog
134 lines
3.1 KiB
Verilog
/* verilator lint_off STMTDLY */
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module dv_ctrl(/*AUTOARG*/
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// Outputs
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nreset, clk1, clk2, start, vdd, vss,
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// Inputs
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dut_active, stim_done, test_done
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);
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parameter CFG_CLK1_PERIOD = 10;
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parameter CFG_CLK1_PHASE = CFG_CLK1_PERIOD/2;
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parameter CFG_CLK2_PERIOD = 20;
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parameter CFG_CLK2_PHASE = CFG_CLK2_PERIOD/2;
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parameter CFG_TIMEOUT = 5000;
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output nreset; // async active low reset
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output clk1; // main clock
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output clk2; // secondary clock
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output start; // start test (level)
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output vdd; // driving vdd
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output vss; // driving vss
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input dut_active; // reset sequence is done
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input stim_done; //stimulus is done
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input test_done; //test is done
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//signal declarations
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reg vdd;
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reg vss;
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reg nreset;
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reg start;
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reg clk1=0;
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reg clk2=0;
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reg [6:0] clk1_phase;
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reg [6:0] clk2_phase;
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integer seed,r;
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reg [1023:0] testname;
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//#################################
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// RANDOM NUMBER GENERATOR
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// (SEED SUPPLIED EXERNALLY)
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//#################################
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initial
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begin
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r=$value$plusargs("SEED=%s", seed);
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r=$value$plusargs("TESTNAME=%s", testname[1023:0]);
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$display("SEED=%d", seed);
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`ifdef CFG_RANDOM
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clk1_phase = 1 + {$random(seed)}; //generate random values
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clk2_phase = 1 + {$random(seed)}; //generate random values
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`else
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clk1_phase = CFG_CLK1_PHASE;
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clk2_phase = CFG_CLK2_PHASE;
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`endif
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$display("clk1_phase=%d clk2_phase=%d", clk1_phase,clk2_phase);
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end
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//#################################
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//CLK1 GENERATOR
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//#################################
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always
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#(clk1_phase) clk1 = ~clk1; //add one to avoid "DC" state
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//#################################
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//CLK2 GENERATOR
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//#################################
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always
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#(clk2_phase) clk2 = ~clk2;
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//#################################
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//ASYNC
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//#################################
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initial
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begin
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#(1)
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nreset = 'b0;
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vdd = 'b0;
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vss = 'b0;
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#(clk1_phase * 10 + 100) //ramping voltage
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vdd = 'bx;
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#(clk1_phase * 10 + 100) //voltage is safe
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vdd = 'b1;
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#(clk1_phase * 40 + 100) //hold reset for 20 clk cycles
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nreset = 'b1;
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end
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//#################################
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//SYNCHRONOUS STIMULUS
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//#################################
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//START TEST
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always @ (posedge clk1 or negedge nreset)
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if(!nreset)
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start <= 1'b0;
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else if(dut_active)
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start <= 1'b1;
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//STOP SIMULATION
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always @ (posedge clk1)
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if(stim_done & test_done)
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begin
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//$display("TEST DONE");
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//$finish;
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end
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//#################################
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// TIMEOUT
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//#################################
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initial
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begin
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#(CFG_TIMEOUT)
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$display("TEST %0s FAILED ON TIMEOUT",testname);
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$finish;
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end
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//#################################
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//WAVEFORM DUMP
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//#################################
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`ifndef VERILATOR
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initial
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begin
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$dumpfile("waveform.vcd");
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$dumpvars(0, dv_top);
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end
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`endif
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endmodule // dv_ctrl
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