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142 lines
3.8 KiB
Verilog
142 lines
3.8 KiB
Verilog
module oh_fifo_async (/*AUTOARG*/
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// Outputs
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dout, full, prog_full, empty, rd_count,
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// Inputs
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nreset, wr_clk, wr_en, din, rd_clk, rd_en
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);
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//#####################################################################
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//# INTERFACE
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//#####################################################################
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parameter DW = 104; // FIFO width
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parameter DEPTH = 32; // FIFO depth (entries)
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parameter TYPE = "XILINX"; // "XILINX" or "ALTERA"
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parameter WAIT = 0; // assert random prog_full wait
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parameter CW = $clog2(DEPTH);// binary read count width
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//clk/reset
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input nreset; // async reset
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//write port
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input wr_clk; // write clock
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input wr_en; // write fifo
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input [DW-1:0] din; // data to write
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//read port
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input rd_clk; // read clock
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input rd_en; // read fifo
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output [DW-1:0] dout; // output data (next cycle)
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//status
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output full; // fifo is full
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output prog_full; // fifo reaches full threshold
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output empty; // fifo is empty
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output [CW-1:0] rd_count; // valid entries in fifo
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//#####################################################################
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//# BODY
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//#####################################################################
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//local wires
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wire fifo_prog_full;
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wire wait_random;
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assign prog_full = fifo_prog_full | wait_random;
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generate
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if(TYPE=="GENERIC") begin : basic
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oh_fifo_async_model
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#(.DEPTH(DEPTH),
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.DW(DW))
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fifo_model (
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// Outputs
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.full (full),
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.prog_full (fifo_prog_full),
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.dout (dout[DW-1:0]),
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.empty (empty),
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.rd_data_count (rd_count[CW-1:0]),
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// Inputs
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.rst (~nreset),
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.wr_clk (wr_clk),
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.rd_clk (rd_clk),
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.wr_en (wr_en),
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.din (din[DW-1:0]),
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.rd_en (rd_en));
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end
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else if (TYPE=="XILINX") begin : xilinx
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if((DW==104) & (DEPTH==32))
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begin
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fifo_async_104x32 fifo (
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// Outputs
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.full (full),
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.prog_full (fifo_prog_full),
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.dout (dout[DW-1:0]),
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.empty (empty),
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.rd_data_count (rd_count[CW-1:0]),
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// Inputs
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.rst (~nreset),
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.wr_clk (wr_clk),
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.rd_clk (rd_clk),
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.wr_en (wr_en),
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.din (din[DW-1:0]),
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.rd_en (rd_en));
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end // if ((DW==104) & (DEPTH==32))
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end // block: xilinx
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endgenerate
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//Random wait generator
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generate
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if(WAIT>0)
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begin
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reg [7:0] wait_counter;
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always @ (posedge wr_clk or negedge nreset)
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if(~nreset)
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wait_counter[7:0] <= 'b0;
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else
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wait_counter[7:0] <= wait_counter+1'b1;
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assign wait_random = (|wait_counter[4:0]);//(|wait_counter[3:0]);//1'b0;
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end
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else
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begin
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assign wait_random = 1'b0;
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end // else: !if(WAIT)
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endgenerate
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endmodule // oh_fifo_async
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// Local Variables:
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// verilog-library-directories:("." "../fpga/" "../dv")
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// End:
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module oh_fifo_async_model
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(/*AUTOARG*/
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// Outputs
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dout, empty, rd_count, full, prog_full,
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// Inputs
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nreset, wr_clk, wr_en, din, rd_clk, rd_en
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);
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parameter DW = 104; //Fifo width
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parameter DEPTH = 1; //Fifo depth (entries)
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parameter CW = $clog2(DEPTH); //FIFO address width (for model)
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//common reset
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input nreset; //asynchronous active low reset
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//fifo write
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input wr_clk; //write clock
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input wr_en;
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input [DW-1:0] din;
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//fifo read
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input rd_clk; //read clock
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input rd_en;
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output [DW-1:0] dout;
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//status
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output empty;
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output [CW-1:0] rd_count;
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output full;
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output prog_full;
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endmodule // oh_fifo_async_model
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