mirror of
https://github.com/aolofsson/oh.git
synced 2025-01-17 20:02:53 +08:00
fd7aff5dd8
- Don't fight the tools - No way to remove these warnings and I don't want to have to tell everyone to include maging "don't output this kind of warning flags" that are global to a project...that's just bad practice. - Didn't take many minutes to remove these warnings and now synthesis runs through with 0 warnings ... much cleaner.. inspires more confidence
43 lines
792 B
Verilog
43 lines
792 B
Verilog
module oh_mux4(/*AUTOARG*/
|
|
// Outputs
|
|
out,
|
|
// Inputs
|
|
in0, in1, in2, in3, sel0, sel1, sel2, sel3
|
|
);
|
|
|
|
parameter DW=99;
|
|
|
|
//data inputs
|
|
input [DW-1:0] in0;
|
|
input [DW-1:0] in1;
|
|
input [DW-1:0] in2;
|
|
input [DW-1:0] in3;
|
|
|
|
//select inputs
|
|
input sel0;
|
|
input sel1;
|
|
input sel2;
|
|
input sel3;
|
|
|
|
output [DW-1:0] out;
|
|
|
|
wire error;
|
|
|
|
|
|
assign out[DW-1:0] = ({(DW){sel0}} & in0[DW-1:0] |
|
|
{(DW){sel1}} & in1[DW-1:0] |
|
|
{(DW){sel2}} & in2[DW-1:0] |
|
|
{(DW){sel3}} & in3[DW-1:0]);
|
|
|
|
|
|
assign error = (sel0 | sel1 | sel2 | sel3) &
|
|
~(sel0 ^ sel1 ^ sel2 ^ sel3);
|
|
|
|
`ifdef TARGET_SIM
|
|
always @ (posedge error)
|
|
$display ("ERROR at in oh_mux4 %m at ",$time);
|
|
`endif
|
|
|
|
endmodule // oh_mux4
|
|
|