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54 lines
1.2 KiB
Verilog
54 lines
1.2 KiB
Verilog
/*###########################################################################
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*#Clock buffer with built in divider
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*###########################################################################
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*
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* Division ratios: 1,2,3,4,5,6,7,8, and bypass division ratings
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*
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* BUFRs can drive:
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* -I/O logic
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* -logic resources
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*
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* BUFRs can be driven by:
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* -SRCCs and MRCCs in the same clock region
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* -MRCCs in an adjacent clock region using BUFMRs
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* -MMCMs clock outputs 0-3 driving the HPC in the same clock region
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* -MMCMs clock outputs 0-3
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* -General interconnect
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*
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* Input to Output Delay (Zynq7010/7020): 1.04/0.80/0.64 (-1/-2/-3 grade)
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*
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*/
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module BUFR (/*AUTOARG*/
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// Outputs
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O,
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// Inputs
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I, CE, CLR
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);
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parameter BUFR_DIVIDE=4;
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parameter SIM_DEVICE=0;
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input I; //clock input
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input CE; //async output clock enable
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input CLR; //async clear for divider logic
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output O; //clock output
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//assign O=I & CE & ~CLR;
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//TODO: need to paraemtrize this!!!
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clock_divider clock_divider (
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// Outputs
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.clkout (O),
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// Inputs
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.clkin (I),
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.divcfg (4'b0010),//div4
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.reset (CLR)
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);
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endmodule // IBUFDS
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// Local Variables:
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// verilog-library-directories:("../../common/hdl")
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// End:
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