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69 lines
2.3 KiB
Verilog
69 lines
2.3 KiB
Verilog
/* verilator lint_off WIDTH */
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module IDELAYE2 (/*AUTOARG*/
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// Outputs
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CNTVALUEOUT, DATAOUT,
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// Inputs
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C, CE, CINVCTRL, CNTVALUEIN, DATAIN, IDATAIN, INC, LD, LDPIPEEN,
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REGRST
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);
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parameter CINVCTRL_SEL = "FALSE"; // Enable clock inversion
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parameter DELAY_SRC = "IDATAIN"; // Delay input
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parameter HIGH_PERFORMANCE_MODE = "FALSE";// Reduced jitter
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parameter IDELAY_TYPE = "FIXED"; // Type of delay line
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parameter integer IDELAY_VALUE = 0; // Input delay tap setting
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parameter [0:0] IS_C_INVERTED = 1'b0; //
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parameter [0:0] IS_DATAIN_INVERTED = 1'b0; //
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parameter [0:0] IS_IDATAIN_INVERTED = 1'b0; //
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parameter PIPE_SEL = "FALSE"; // Select pipelined mode
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parameter real REFCLK_FREQUENCY = 200.0; // Ref clock frequency
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parameter SIGNAL_PATTERN = "DATA"; // Input signal type
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`ifdef XIL_TIMING
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parameter LOC = "UNPLACED";
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parameter integer SIM_DELAY_D = 0;
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localparam DELAY_D = (IDELAY_TYPE == "VARIABLE") ? SIM_DELAY_D : 0;
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`endif // ifdef XIL_TIMING
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`ifndef XIL_TIMING
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integer DELAY_D=0;
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`endif // ifndef XIL_TIMING
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output [4:0] CNTVALUEOUT; // count value for monitoring tap value
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output DATAOUT; // delayed data
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input C; // clock input for variable mode
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input CE; // enable increment/decrement function
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input CINVCTRL; // dynamically inverts clock polarity
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input [4:0] CNTVALUEIN; // counter value for tap delay
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input DATAIN; // data input from FGPA logic
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input IDATAIN; // data input from IBUF
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input INC; // increment tap delay
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input LD; // loads the delay primitive
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input LDPIPEEN; // enables the pipeline register delay
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input REGRST; // reset for pipeline register
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parameter real tap = 1 / (32 * 2 * (REFCLK_FREQUENCY/1000));
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reg [4:0] idelay_reg=5'b0;
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reg DATAOUT;
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always @ (posedge C)
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if(LD)
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begin
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idelay_reg[4:0] <= CNTVALUEIN[4:0];
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end
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//Variable delay
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always @ (IDATAIN)
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DATAOUT <= #(idelay_reg * tap) IDATAIN;
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//not modeled
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assign CNTVALUEOUT=5'b0;
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endmodule // IDELAYE2
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